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Searched refs:BIT5 (Results 1 – 25 of 36) sorted by relevance

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/openbmc/linux/drivers/scsi/
H A Ddc395x.h71 #define BIT5 0x00000020 macro
134 #define SRB_ERROR BIT5
139 #define RESIDUAL_VALID BIT5
170 #define EN_TAG_QUEUEING BIT5
597 #define LUN_CHECK BIT5
/openbmc/linux/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_hw.h102 #define SCR_NoSKMC BIT5
117 #define IMR_HCCADOK BIT5
125 #define TP_POLL_CQ BIT5
186 #define RRSR_9M BIT5
/openbmc/linux/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h47 …MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b…
76 …, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b…
151 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK …
182 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*reset dual TS…
H A Drtl8723b_spec.h170 #define BIT_BCN_PORT_SEL BIT5
209 #define IMR_BKDOK_8723B BIT5 /* AC_BK DMA OK */
H A Dhal_com_reg.h525 #define HSISR_SPS_OCP_INT BIT5
552 #define RRSR_9M BIT5
646 #define CAM_USEDK BIT5
710 #define IMR_TBDER BIT5 /* For 92C, Transmit Beacon Error Interrupt */
758 #define RCR_APWRMGT BIT5 /* Accept power management packet */
1283 #define SDIO_HIMR_RXFOVW_MSK BIT5
1305 #define SDIO_HISR_RXFOVW BIT5
H A Dosdep_service.h22 #define BIT5 0x00000020 macro
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h262 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
383 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0 \
416 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
466 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
619 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
/openbmc/libcper/include/libcper/
H A DCper.h190 #define EFI_ERROR_SECTION_FLAGS_LATENT_ERROR BIT5
292 #define EFI_GENERIC_ERROR_PROC_LEVEL_VALID BIT5
433 #define EFI_CACHE_CHECK_PRECISE_IP_VALID BIT5
486 #define EFI_TLB_CHECK_PRECISE_IP_VALID BIT5
537 #define EFI_BUS_CHECK_PRECISE_IP_VALID BIT5
612 #define EFI_MS_CHECK_OVERFLOW_VALID BIT5
882 #define EFI_PLATFORM_MEMORY_MODULE_VALID BIT5
958 #define EFI_PLATFORM_MEMORY2_MODULE_VALID BIT5
1036 #define EFI_PCIE_ERROR_BRIDGE_CRL_STS_VALID BIT5
1120 #define EFI_PCI_PCIX_BUS_ERROR_COMMAND_VALID BIT5
/openbmc/linux/drivers/video/fbdev/via/
H A Ddvi.c62 BIT5 + BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
66 viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5); in viafb_tmds_trasmitter_identify()
396 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
408 viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
H A Dhw.c1696 viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5); in device_screen_off()
1702 viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5); in device_screen_on()
1713 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1717 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); in set_display_channel()
1720 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); in set_display_channel()
1725 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1728 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); in set_display_channel()
2065 p_gfx_dpa_setting->DVP0DataDri_S1, BIT5); in viafb_set_dpa_gfx()
H A Dshare.h19 #define BIT5 0x20 macro
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbt_precomp.h36 #define BIT5 0x00000020 macro
H A Dhalbtc8192e2ant.h9 #define BT_INFO_8192E_2ANT_B_HID BIT5
H A Dhalbtc8821a1ant.h10 #define BT_INFO_8821A_1ANT_B_HID BIT5
H A Dhalbtc8821a2ant.h10 #define BT_INFO_8821A_2ANT_B_HID BIT5
H A Dhalbtc8723b2ant.h12 #define BT_INFO_8723B_2ANT_B_HID BIT5
H A Dhalbtc8723b1ant.h9 #define BT_INFO_8723B_1ANT_B_HID BIT5
/openbmc/linux/drivers/staging/rtl8723bs/hal/
H A DHalBtc8723b2Ant.h10 #define BT_INFO_8723B_2ANT_B_HID BIT5
H A DHalBtc8723b1Ant.h10 #define BT_INFO_8723B_1ANT_B_HID BIT5
H A DHal8723BReg.h398 #define IMR_BKDOK_8723B BIT5 /* AC_BK DMA OK */
H A Dodm.h370 ODM_BB_CCK_PD = BIT5,
447 ODM_WM_AUTO = BIT5,
/openbmc/linux/drivers/staging/rtl8192e/
H A Drtl819x_Qos.h15 #define BIT5 0x00000020 macro
/openbmc/linux/drivers/tty/
H A Dsynclink_gt.c390 #define IRQ_DCD BIT5
2133 if (status & (BIT5 + BIT4)) { in isr_rdma()
2158 if (status & (BIT5 + BIT4 + BIT3)) { in isr_tdma()
4039 case 7: val |= BIT5; break; in async_mode()
4040 case 8: val |= BIT5 + BIT4; break; in async_mode()
4079 case 7: val |= BIT5; break; in async_mode()
4080 case 8: val |= BIT5 + BIT4; break; in async_mode()
4203 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; in sync_mode()
4205 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; in sync_mode()
4291 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ in sync_mode()
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/openbmc/linux/include/uapi/linux/
H A Dsynclink.h24 #define BIT5 0x0020 macro
/openbmc/linux/lib/zstd/common/
H A Dzstd_internal.h68 #define BIT5 32 macro

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