Home
last modified time | relevance | path

Searched refs:ARM_CP_STATE_AA64 (Results 1 – 7 of 7) sorted by relevance

/openbmc/qemu/target/arm/tcg/
H A Dcpu64.c480 { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
485 { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
488 { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64,
491 { .name = "ATCR_EL12", .state = ARM_CP_STATE_AA64,
494 { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64,
497 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
501 { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
505 { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
513 { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64,
516 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
[all …]
/openbmc/qemu/target/arm/
H A Dcortex-regs.c30 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
38 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
47 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
53 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
59 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
65 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
H A Dhelper.c2108 { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO,
2121 { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
2135 { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
2148 { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64,
2160 { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
2171 { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
2185 { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
2198 { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
2209 { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64,
2220 { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
[all …]
H A Dcpregs.h241 ARM_CP_STATE_AA64 = 1, enumerator
1059 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); in cpreg_field_is_64bit()
1090 return ri->state == ARM_CP_STATE_AA64 && in arm_cpreg_in_idspace()
H A Ddebug_helper.c951 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
970 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
1074 { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
H A Dgdbstub.c275 if (ri->state == ARM_CP_STATE_AA64) { in arm_register_sysreg_for_feature()
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c2506 { .name = "ICC_SGI1R_EL1", .state = ARM_CP_STATE_AA64,
2518 { .name = "ICC_ASGI1R_EL1", .state = ARM_CP_STATE_AA64,
2530 { .name = "ICC_SGI0R_EL1", .state = ARM_CP_STATE_AA64,