/openbmc/qemu/tests/tcg/xtensa/ |
H A D | test_shift.S | 5 .macro test_shift prefix, dst, src, v, imm argument 6 \prefix\()_set \dst, \src, \v, \imm 7 \prefix\()_ver \dst, \v, \imm 10 .macro test_shift_sd prefix, v, imm argument 11 test_shift \prefix, a3, a2, \v, \imm 12 test_shift \prefix, a2, a2, \v, \imm 32 .macro slli_set dst, src, v, imm argument 34 slli \dst, \src, \imm 37 .macro slli_ver dst, v, imm argument 39 movi a3, ((\v) << (\imm)) & 0xffffffff [all …]
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H A D | test_sar.S | 5 .macro test_sar prefix, imm argument 6 \prefix\()_set \imm 7 \prefix\()_ver \imm 22 .macro sar_set imm argument 23 movi a2, \imm 27 .macro sar_ver imm argument 29 movi a2, \imm & 0x3f 37 .macro ssr_set imm argument 38 movi a2, \imm 42 .macro ssr_ver imm argument [all …]
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/openbmc/linux/arch/powerpc/net/ |
H A D | bpf_jit_comp32.c | 305 s32 imm = insn[i].imm; in bpf_jit_build_body() local 315 insn[i - 1].dst_reg == insn[i].dst_reg && insn[i - 1].imm != 1) { in bpf_jit_build_body() 367 imm = -imm; in bpf_jit_build_body() 370 if (!imm) { in bpf_jit_build_body() 372 } else if (IMM_HA(imm) & 0xffff) { in bpf_jit_build_body() 373 EMIT(PPC_RAW_ADDIS(dst_reg, src2_reg, IMM_HA(imm))); in bpf_jit_build_body() 376 if (IMM_L(imm)) in bpf_jit_build_body() 377 EMIT(PPC_RAW_ADDI(dst_reg, src2_reg, IMM_L(imm))); in bpf_jit_build_body() 380 imm = -imm; in bpf_jit_build_body() 383 if (!imm) { in bpf_jit_build_body() [all …]
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H A D | bpf_jit_comp64.c | 384 s32 imm = insn[i].imm; in bpf_jit_build_body() local 428 if (!imm) { in bpf_jit_build_body() 430 } else if (imm >= -32768 && imm < 32768) { in bpf_jit_build_body() 431 EMIT(PPC_RAW_ADDI(dst_reg, dst_reg, IMM_L(imm))); in bpf_jit_build_body() 433 PPC_LI32(tmp1_reg, imm); in bpf_jit_build_body() 439 if (!imm) { in bpf_jit_build_body() 441 } else if (imm > -32768 && imm <= 32768) { in bpf_jit_build_body() 442 EMIT(PPC_RAW_ADDI(dst_reg, dst_reg, IMM_L(-imm))); in bpf_jit_build_body() 444 PPC_LI32(tmp1_reg, imm); in bpf_jit_build_body() 457 if (imm >= -32768 && imm < 32768) in bpf_jit_build_body() [all …]
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/openbmc/linux/arch/arm/net/ |
H A D | bpf_jit_32.h | 164 #define _AL3_I(op, rd, rn, imm) ((op ## _I) | (rd) << 12 | (rn) << 16 | (imm)) argument 170 #define ARM_ADD_I(rd, rn, imm) _AL3_I(ARM_INST_ADD, rd, rn, imm) argument 171 #define ARM_ADDS_I(rd, rn, imm) _AL3_I(ARM_INST_ADDS, rd, rn, imm) argument 173 #define ARM_ADC_I(rd, rn, imm) _AL3_I(ARM_INST_ADC, rd, rn, imm) argument 177 #define ARM_AND_I(rd, rn, imm) _AL3_I(ARM_INST_AND, rd, rn, imm) argument 180 #define ARM_BIC_I(rd, rn, imm) _AL3_I(ARM_INST_BIC, rd, rn, imm) argument 187 #define ARM_CMP_I(rn, imm) _AL3_I(ARM_INST_CMP, 0, rn, imm) argument 190 #define ARM_EOR_I(rd, rn, imm) _AL3_I(ARM_INST_EOR, rd, rn, imm) argument 195 #define ARM_LDR_R_SI(rt, rn, rm, type, imm) \ argument 198 | (imm) << 7 | (type) << 5 | (rm)) [all …]
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/openbmc/linux/arch/loongarch/kernel/ |
H A D | inst.c | 17 unsigned int imm = insn.reg1i20_format.immediate; in simu_pc() local 26 regs->regs[rd] = pc + sign_extend64(imm << 2, 21); in simu_pc() 29 regs->regs[rd] = pc + sign_extend64(imm << 12, 31); in simu_pc() 32 regs->regs[rd] = pc + sign_extend64(imm << 18, 37); in simu_pc() 35 regs->regs[rd] = pc + sign_extend64(imm << 12, 31); in simu_pc() 48 unsigned int imm, imm_l, imm_h, rd, rj; in simu_branch() local 86 imm = insn.reg2i16_format.immediate; in simu_branch() 92 regs->csr_era = pc + sign_extend64(imm << 2, 17); in simu_branch() 98 regs->csr_era = pc + sign_extend64(imm << 2, 17); in simu_branch() 104 regs->csr_era = pc + sign_extend64(imm << 2, 17); in simu_branch() [all …]
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/openbmc/qemu/target/rx/ |
H A D | insns.decode | 25 &ri rd imm 27 &rri rd imm rs2 29 &mi rs ld mi imm 44 @b2_rds_li .... .... .... rd:4 &rri rs2=%b2_r_0 imm=%b2_li_8 45 @b2_rds_uimm4 .... .... imm:4 rd:4 &rri rs2=%b2_r_0 46 @b2_rs2_uimm4 .... .... imm:4 rs2:4 &rri rd=0 47 @b2_rds_imm5 .... ... imm:5 rd:4 &rri rs2=%b2_r_0 48 @b2_rd_rs_li .... .... rs2:4 rd:4 &rri imm=%b2_li_8 50 @b2_ld_imm3 .... .. ld:2 rs:4 . imm:3 &mi mi=4 64 &rri rs2=%b3_r_0 imm=%b3_li_10 [all …]
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/openbmc/linux/tools/include/linux/ |
H A D | filter.h | 40 .imm = 0 }) 48 .imm = 0 }) 58 .imm = IMM }) 66 .imm = IMM }) 76 .imm = LEN }) 86 .imm = 0 }) 94 .imm = 0 }) 104 .imm = IMM }) 112 .imm = IMM }) 122 .imm = IMM }) [all …]
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/openbmc/linux/samples/bpf/ |
H A D | bpf_insn.h | 16 .imm = 0 }) 24 .imm = 0 }) 34 .imm = IMM }) 42 .imm = IMM }) 52 .imm = 0 }) 60 .imm = 0 }) 70 .imm = IMM }) 78 .imm = IMM }) 90 .imm = (__u32) (IMM) }), \ 96 .imm = ((__u64) (IMM)) >> 32 }) [all …]
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/openbmc/linux/arch/mips/net/ |
H A D | bpf_jit_comp.c | 192 void emit_mov_i(struct jit_context *ctx, u8 dst, s32 imm) in emit_mov_i() argument 194 if (imm >= -0x8000 && imm <= 0x7fff) { in emit_mov_i() 195 emit(ctx, addiu, dst, MIPS_R_ZERO, imm); in emit_mov_i() 197 emit(ctx, lui, dst, (s16)((u32)imm >> 16)); in emit_mov_i() 198 emit(ctx, ori, dst, dst, (u16)(imm & 0xffff)); in emit_mov_i() 211 bool valid_alu_i(u8 op, s32 imm) in valid_alu_i() argument 224 return imm >= -0x8000 && imm <= 0x7fff; in valid_alu_i() 229 return imm >= -0x7fff && imm <= 0x8000; in valid_alu_i() 234 return imm >= 0 && imm <= 0xffff; in valid_alu_i() 237 return imm == 0 || (imm > 0 && is_power_of_2(imm)); in valid_alu_i() [all …]
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H A D | bpf_jit_comp32.c | 174 static void emit_mov_se_i64(struct jit_context *ctx, const u8 dst[], s32 imm) in emit_mov_se_i64() argument 176 emit_mov_i(ctx, lo(dst), imm); in emit_mov_se_i64() 177 if (imm < 0) in emit_mov_se_i64() 202 const u8 dst[], s32 imm, u8 op) in emit_alu_i64() argument 210 if (imm > S32_MIN && imm < 0) in emit_alu_i64() 214 imm = -imm; in emit_alu_i64() 218 imm = -imm; in emit_alu_i64() 223 emit_mov_i(ctx, src, imm); in emit_alu_i64() 231 if (imm < 0) in emit_alu_i64() 239 if (imm < 0) in emit_alu_i64() [all …]
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/openbmc/linux/kernel/bpf/ |
H A D | disasm.c | 23 insn->imm >= 0 && insn->imm < __BPF_FUNC_MAX_ID && in __func_get_name() 24 func_id_str[insn->imm]) in __func_get_name() 25 return func_id_str[insn->imm]; in __func_get_name() 36 snprintf(buff, len, "%+d", insn->imm); in __func_get_name() 145 insn->imm, insn->dst_reg); in print_bpf_end_insn() 154 insn->imm, insn->dst_reg); in print_bpf_bswap_insn() 202 insn->imm); in print_bpf_insn() 212 (insn->imm == BPF_ADD || insn->imm == BPF_AND || in print_bpf_insn() 213 insn->imm == BPF_OR || insn->imm == BPF_XOR)) { in print_bpf_insn() 218 bpf_alu_string[BPF_OP(insn->imm) >> 4], in print_bpf_insn() [all …]
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/openbmc/qemu/target/riscv/ |
H A D | insn16.decode | 57 &i imm rs1 rd !extern 58 &s imm rs1 rs2 !extern 59 &j imm rd !extern 60 &b imm rs2 rs1 !extern 61 &u imm rd !extern 71 @ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd 72 @cl_q ... . ..... ..... .. &i imm=%uimm_cl_q rs1=%rs1_3 rd=%rs2_3 73 @cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3 74 @cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3 76 @cs_q ... ... ... .. ... .. &s imm=%uimm_cl_q rs1=%rs1_3 rs2=%rs2_3 [all …]
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/openbmc/linux/tools/testing/selftests/bpf/ |
H A D | disasm.c | 23 insn->imm >= 0 && insn->imm < __BPF_FUNC_MAX_ID && in __func_get_name() 24 func_id_str[insn->imm]) in __func_get_name() 25 return func_id_str[insn->imm]; in __func_get_name() 36 snprintf(buff, len, "%+d", insn->imm); in __func_get_name() 145 insn->imm, insn->dst_reg); in print_bpf_end_insn() 154 insn->imm, insn->dst_reg); in print_bpf_bswap_insn() 202 insn->imm); in print_bpf_insn() 212 (insn->imm == BPF_ADD || insn->imm == BPF_AND || in print_bpf_insn() 213 insn->imm == BPF_OR || insn->imm == BPF_XOR)) { in print_bpf_insn() 218 bpf_alu_string[BPF_OP(insn->imm) >> 4], in print_bpf_insn() [all …]
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/openbmc/qemu/target/avr/ |
H A D | disas.c | 135 INSN(ADIW, "r%d:r%d, %d", a->rd + 1, a->rd, a->imm) 137 INSN(SUBI, "r%d, %d", a->rd, a->imm) 139 INSN(SBCI, "r%d, %d", a->rd, a->imm) 140 INSN(SBIW, "r%d:r%d, %d", a->rd + 1, a->rd, a->imm) 142 INSN(ANDI, "r%d, %d", a->rd, a->imm) 144 INSN(ORI, "r%d, %d", a->rd, a->imm) 156 INSN(DES, "%d", a->imm) 161 INSN(RJMP, ".%+d", a->imm * 2) 164 INSN(JMP, "0x%x", a->imm * 2) 165 INSN(RCALL, ".%+d", a->imm * 2) [all …]
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/openbmc/linux/arch/riscv/net/ |
H A D | bpf_jit.h | 266 u32 imm; in rv_j_insn() local 268 imm = (imm20_1 & 0x80000) | ((imm20_1 & 0x3ff) << 9) | in rv_j_insn() 271 return (imm << 12) | (rd << 7) | opcode; in rv_j_insn() 291 u32 imm; in rv_ci_insn() local 293 imm = ((imm6 & 0x20) << 7) | ((imm6 & 0x1f) << 2); in rv_ci_insn() 294 return (funct3 << 13) | (rd << 7) | op | imm; in rv_ci_insn() 329 u32 imm; in rv_cb_insn() local 331 imm = ((imm6 & 0x20) << 7) | ((imm6 & 0x1f) << 2); in rv_cb_insn() 332 return (funct3 << 13) | (funct2 << 10) | ((rd & 0x7) << 7) | op | imm; in rv_cb_insn() 608 u32 imm; in rvc_addi4spn() local [all …]
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H A D | bpf_jit_comp32.c | 111 static void emit_imm(const s8 rd, s32 imm, struct rv_jit_context *ctx) in emit_imm() argument 113 u32 upper = (imm + (1 << 11)) >> 12; in emit_imm() 114 u32 lower = imm & 0xfff; in emit_imm() 124 static void emit_imm32(const s8 *rd, s32 imm, struct rv_jit_context *ctx) in emit_imm32() argument 127 emit_imm(lo(rd), imm, ctx); in emit_imm32() 130 if (imm >= 0) in emit_imm32() 243 static void emit_alu_i64(const s8 *dst, s32 imm, in emit_alu_i64() argument 251 emit_imm32(rd, imm, ctx); in emit_alu_i64() 254 if (is_12b_int(imm)) { in emit_alu_i64() 255 emit(rv_andi(lo(rd), lo(rd), imm), ctx); in emit_alu_i64() [all …]
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/openbmc/linux/arch/arm64/net/ |
H A D | bpf_jit.h | 73 #define A64_LS_IMM(Rt, Rn, imm, size, type) \ argument 74 aarch64_insn_gen_load_store_imm(Rt, Rn, imm, \ 77 #define A64_STRBI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 8, STORE) argument 78 #define A64_LDRBI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 8, LOAD) argument 79 #define A64_LDRSBI(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 8, SIGNED_LOAD) argument 80 #define A64_STRHI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 16, STORE) argument 81 #define A64_LDRHI(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 16, LOAD) argument 82 #define A64_LDRSHI(Xt, Xn, imm) A64_LS_IMM(Xt, Xn, imm, 16, SIGNED_LOAD) argument 83 #define A64_STR32I(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 32, STORE) argument 84 #define A64_LDR32I(Wt, Xn, imm) A64_LS_IMM(Wt, Xn, imm, 32, LOAD) argument [all …]
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/openbmc/qemu/target/arm/tcg/ |
H A D | t16.decode | 25 &s_rri_rot !extern s rn rd imm rot 29 &ri !extern rd imm 31 &i !extern imm 33 &ldst_ri !extern p w u rn rt imm 37 &ci !extern cond imm 62 RSB_rri 010000 1001 rn:3 rd:3 &s_rri_rot %s imm=0 rot=0 88 @ldst_ri_1 ..... imm:5 rn:3 rt:3 \ 91 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x4 102 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x2 111 &ldst_ri p=1 w=0 u=1 imm=%imm8_0x4 [all …]
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/openbmc/qemu/tests/qemu-iotests/ |
H A D | 026.out.nocache | 6 Event: l1_update; errno: 5; imm: off; once: on; write 11 Event: l1_update; errno: 5; imm: off; once: on; write -b 16 Event: l1_update; errno: 5; imm: off; once: off; write 23 Event: l1_update; errno: 5; imm: off; once: off; write -b 30 Event: l1_update; errno: 28; imm: off; once: on; write 35 Event: l1_update; errno: 28; imm: off; once: on; write -b 40 Event: l1_update; errno: 28; imm: off; once: off; write 47 Event: l1_update; errno: 28; imm: off; once: off; write -b 54 Event: l2_load; errno: 5; imm: off; once: on; write 62 Event: l2_load; errno: 5; imm: off; once: on; write -b [all …]
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H A D | 026.out | 6 Event: l1_update; errno: 5; imm: off; once: on; write 11 Event: l1_update; errno: 5; imm: off; once: on; write -b 16 Event: l1_update; errno: 5; imm: off; once: off; write 23 Event: l1_update; errno: 5; imm: off; once: off; write -b 30 Event: l1_update; errno: 28; imm: off; once: on; write 35 Event: l1_update; errno: 28; imm: off; once: on; write -b 40 Event: l1_update; errno: 28; imm: off; once: off; write 47 Event: l1_update; errno: 28; imm: off; once: off; write -b 54 Event: l2_load; errno: 5; imm: off; once: on; write 62 Event: l2_load; errno: 5; imm: off; once: on; write -b [all …]
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/openbmc/qemu/hw/mips/ |
H A D | bootloader.c | 104 bl_reg rs, bl_reg rt, uint16_t imm) in bl_gen_i_type() argument 112 insn = deposit32(insn, 0, 16, imm); in bl_gen_i_type() 159 static void bl_gen_lui(void **p, bl_reg rt, uint16_t imm) in bl_gen_lui() argument 162 bl_gen_i_type(p, 0x0f, 0, rt, imm); in bl_gen_lui() 178 static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm) in bl_gen_ori() argument 180 bl_gen_i_type(p, 0x0d, rs, rt, imm); in bl_gen_ori() 216 static void bl_gen_li(void **p, bl_reg rt, uint32_t imm) in bl_gen_li() argument 219 bl_gen_lui_nm(p, rt, extract32(imm, 12, 20)); in bl_gen_li() 220 bl_gen_ori_nm(p, rt, rt, extract32(imm, 0, 12)); in bl_gen_li() 222 bl_gen_lui(p, rt, extract32(imm, 16, 16)); in bl_gen_li() [all …]
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/openbmc/linux/arch/arm/probes/kprobes/ |
H A D | checkers-common.c | 34 int imm = insn & 0xff; in checker_stack_use_imm_0xx() local 35 asi->stack_space = imm; in checker_stack_use_imm_0xx() 47 int imm = insn & 0xff; in checker_stack_use_t32strd() local 48 asi->stack_space = imm << 2; in checker_stack_use_t32strd() 56 int imm = ((insn & 0xf00) >> 4) + (insn & 0xf); in checker_stack_use_imm_x0x() local 57 asi->stack_space = imm; in checker_stack_use_imm_x0x() 66 int imm = insn & 0xfff; in checker_stack_use_imm_xxx() local 67 asi->stack_space = imm; in checker_stack_use_imm_xxx()
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/openbmc/linux/arch/riscv/kernel/ |
H A D | alternative.c | 76 s32 imm; in riscv_alternative_fix_auipc_jalr() local 79 imm = riscv_insn_extract_utype_itype_imm(auipc_insn, jalr_insn); in riscv_alternative_fix_auipc_jalr() 80 imm -= patch_offset; in riscv_alternative_fix_auipc_jalr() 83 riscv_insn_insert_utype_itype_imm(&call[0], &call[1], imm); in riscv_alternative_fix_auipc_jalr() 91 s32 imm; in riscv_alternative_fix_jal() local 94 imm = riscv_insn_extract_jtype_imm(jal_insn); in riscv_alternative_fix_jal() 95 imm -= patch_offset; in riscv_alternative_fix_jal() 98 riscv_insn_insert_jtype_imm(&jal_insn, imm); in riscv_alternative_fix_jal() 134 s32 imm = riscv_insn_extract_jtype_imm(insn); in riscv_alternative_fix_offsets() local 137 if ((alt_ptr + i * sizeof(u32) + imm) >= alt_ptr && in riscv_alternative_fix_offsets() [all …]
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/openbmc/linux/arch/arm64/lib/ |
H A D | insn.c | 113 u32 insn, u64 imm) in aarch64_insn_encode_immediate() argument 124 immlo = (imm & ADR_IMM_LOMASK) << ADR_IMM_LOSHIFT; in aarch64_insn_encode_immediate() 125 imm >>= ADR_IMM_HILOSPLIT; in aarch64_insn_encode_immediate() 126 immhi = (imm & ADR_IMM_HIMASK) << ADR_IMM_HISHIFT; in aarch64_insn_encode_immediate() 127 imm = immlo | immhi; in aarch64_insn_encode_immediate() 141 insn |= (imm & mask) << shift; in aarch64_insn_encode_immediate() 412 unsigned int imm, in aarch64_insn_gen_load_store_imm() argument 425 if (imm & ~(BIT(12 + shift) - BIT(shift))) { in aarch64_insn_gen_load_store_imm() 426 pr_err("%s: invalid imm: %d\n", __func__, imm); in aarch64_insn_gen_load_store_imm() 430 imm >>= shift; in aarch64_insn_gen_load_store_imm() [all …]
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