Searched hist:fd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3 (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/Documentation/devicetree/bindings/sound/ |
| H A D | cs4271.txt | diff fd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3 Mon Dec 10 03:30:04 CST 2012 Daniel Mack <zonque@gmail.com> ALSA: ASoC: cs4271: add optional soft reset workaround
The CS4271 requires its LRCLK and MCLK to be stable before its RESET
line is de-asserted. That also means that clocks cannot be changed
without putting the chip back into hardware reset, which also requires
a complete re-initialization of all registers.
One (undocumented) workaround is to assert and de-assert the PDN bit
in the MODE2 register.
This patch adds a new flag to both the DT bindings as well as to the
platform data to enable that workaround.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Acked-by: Alexander Sverdlin <subaparts@yandex.ru>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| /openbmc/linux/include/sound/ |
| H A D | cs4271.h | diff fd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3 Mon Dec 10 03:30:04 CST 2012 Daniel Mack <zonque@gmail.com> ALSA: ASoC: cs4271: add optional soft reset workaround
The CS4271 requires its LRCLK and MCLK to be stable before its RESET
line is de-asserted. That also means that clocks cannot be changed
without putting the chip back into hardware reset, which also requires
a complete re-initialization of all registers.
One (undocumented) workaround is to assert and de-assert the PDN bit
in the MODE2 register.
This patch adds a new flag to both the DT bindings as well as to the
platform data to enable that workaround.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Acked-by: Alexander Sverdlin <subaparts@yandex.ru>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
| /openbmc/linux/sound/soc/codecs/ |
| H A D | cs4271.c | diff fd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3 Mon Dec 10 03:30:04 CST 2012 Daniel Mack <zonque@gmail.com> ALSA: ASoC: cs4271: add optional soft reset workaround
The CS4271 requires its LRCLK and MCLK to be stable before its RESET
line is de-asserted. That also means that clocks cannot be changed
without putting the chip back into hardware reset, which also requires
a complete re-initialization of all registers.
One (undocumented) workaround is to assert and de-assert the PDN bit
in the MODE2 register.
This patch adds a new flag to both the DT bindings as well as to the
platform data to enable that workaround.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Acked-by: Alexander Sverdlin <subaparts@yandex.ru>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
|