1*c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 267b22517SAlexander Sverdlin /* 367b22517SAlexander Sverdlin * Definitions for CS4271 ASoC codec driver 467b22517SAlexander Sverdlin * 567b22517SAlexander Sverdlin * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru> 667b22517SAlexander Sverdlin */ 767b22517SAlexander Sverdlin 867b22517SAlexander Sverdlin #ifndef __CS4271_H 967b22517SAlexander Sverdlin #define __CS4271_H 1067b22517SAlexander Sverdlin 1167b22517SAlexander Sverdlin struct cs4271_platform_data { 1267b22517SAlexander Sverdlin int gpio_nreset; /* GPIO driving Reset pin, if any */ 1326047e2dSDaniel Mack bool amutec_eq_bmutec; /* flag to enable AMUTEC=BMUTEC */ 14fd23fb9fSDaniel Mack 15fd23fb9fSDaniel Mack /* 16fd23fb9fSDaniel Mack * The CS4271 requires its LRCLK and MCLK to be stable before its RESET 17fd23fb9fSDaniel Mack * line is de-asserted. That also means that clocks cannot be changed 18fd23fb9fSDaniel Mack * without putting the chip back into hardware reset, which also requires 19fd23fb9fSDaniel Mack * a complete re-initialization of all registers. 20fd23fb9fSDaniel Mack * 21fd23fb9fSDaniel Mack * One (undocumented) workaround is to assert and de-assert the PDN bit 22fd23fb9fSDaniel Mack * in the MODE2 register. This workaround can be enabled with the 23fd23fb9fSDaniel Mack * following flag. 24fd23fb9fSDaniel Mack * 25fd23fb9fSDaniel Mack * Note that this is not needed in case the clocks are stable 26fd23fb9fSDaniel Mack * throughout the entire runtime of the codec. 27fd23fb9fSDaniel Mack */ 28fd23fb9fSDaniel Mack bool enable_soft_reset; 2967b22517SAlexander Sverdlin }; 3067b22517SAlexander Sverdlin 3167b22517SAlexander Sverdlin #endif /* __CS4271_H */ 32