Searched hist:e95b19f84d047c195aa3159afb9ba8f300724a9e (Results 1 – 2 of 2) sorted by relevance
| /openbmc/u-boot/arch/arm/include/asm/arch-aspeed/ |
| H A D | scu_ast2600.h | diff e95b19f84d047c195aa3159afb9ba8f300724a9e Thu Nov 18 01:07:25 CST 2021 Dylan Hung <dylan_hung@aspeedtech.com> clk: ast2600: Setup RGMII TX delay according to the DLY32 calculation
There is a duplicate DLY32 delay cell embedded in AST2600 SOC that is
the same with the one used for RGMII clock delay. The delay time of
each tap delay can be measured by the embedded frequency counters
SCU320 and SCU330. So we can set up the TX delay according to the
runtime measured value to cover the chip-to-chip delay time variation.
v2: revise coding style
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I42c6cf09f36baf9ded22accf476cc93ae4991d86
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| /openbmc/u-boot/drivers/clk/aspeed/ |
| H A D | clk_ast2600.c | diff e95b19f84d047c195aa3159afb9ba8f300724a9e Thu Nov 18 01:07:25 CST 2021 Dylan Hung <dylan_hung@aspeedtech.com> clk: ast2600: Setup RGMII TX delay according to the DLY32 calculation
There is a duplicate DLY32 delay cell embedded in AST2600 SOC that is
the same with the one used for RGMII clock delay. The delay time of
each tap delay can be measured by the embedded frequency counters
SCU320 and SCU330. So we can set up the TX delay according to the
runtime measured value to cover the chip-to-chip delay time variation.
v2: revise coding style
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I42c6cf09f36baf9ded22accf476cc93ae4991d86
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