Searched hist:de5191631088e71ba8ed28bb491dafa776058008 (Results 1 – 7 of 7) sorted by relevance
| /openbmc/u-boot/include/configs/ |
| H A D | T4240QDS.h | diff de5191631088e71ba8ed28bb491dafa776058008 Thu Jun 26 01:41:33 CDT 2014 Shaohui Xie <Shaohui.Xie@freescale.com> powerpc/ifc: fix invalid CSn FTIM2.TCH setting
On some platforms, CSn FTIM2.TCH is set to zero which is invalid,
an invalid hold time makes DUT timing variances, whether it works
or not on luck.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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| H A D | C29XPCIE.h | diff de5191631088e71ba8ed28bb491dafa776058008 Thu Jun 26 01:41:33 CDT 2014 Shaohui Xie <Shaohui.Xie@freescale.com> powerpc/ifc: fix invalid CSn FTIM2.TCH setting
On some platforms, CSn FTIM2.TCH is set to zero which is invalid,
an invalid hold time makes DUT timing variances, whether it works
or not on luck.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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| H A D | BSC9132QDS.h | diff de5191631088e71ba8ed28bb491dafa776058008 Thu Jun 26 01:41:33 CDT 2014 Shaohui Xie <Shaohui.Xie@freescale.com> powerpc/ifc: fix invalid CSn FTIM2.TCH setting
On some platforms, CSn FTIM2.TCH is set to zero which is invalid,
an invalid hold time makes DUT timing variances, whether it works
or not on luck.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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| H A D | T208xRDB.h | diff de5191631088e71ba8ed28bb491dafa776058008 Thu Jun 26 01:41:33 CDT 2014 Shaohui Xie <Shaohui.Xie@freescale.com> powerpc/ifc: fix invalid CSn FTIM2.TCH setting
On some platforms, CSn FTIM2.TCH is set to zero which is invalid,
an invalid hold time makes DUT timing variances, whether it works
or not on luck.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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| H A D | B4860QDS.h | diff de5191631088e71ba8ed28bb491dafa776058008 Thu Jun 26 01:41:33 CDT 2014 Shaohui Xie <Shaohui.Xie@freescale.com> powerpc/ifc: fix invalid CSn FTIM2.TCH setting
On some platforms, CSn FTIM2.TCH is set to zero which is invalid,
an invalid hold time makes DUT timing variances, whether it works
or not on luck.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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| H A D | T104xRDB.h | diff de5191631088e71ba8ed28bb491dafa776058008 Thu Jun 26 01:41:33 CDT 2014 Shaohui Xie <Shaohui.Xie@freescale.com> powerpc/ifc: fix invalid CSn FTIM2.TCH setting
On some platforms, CSn FTIM2.TCH is set to zero which is invalid,
an invalid hold time makes DUT timing variances, whether it works
or not on luck.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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| H A D | P1010RDB.h | diff de5191631088e71ba8ed28bb491dafa776058008 Thu Jun 26 01:41:33 CDT 2014 Shaohui Xie <Shaohui.Xie@freescale.com> powerpc/ifc: fix invalid CSn FTIM2.TCH setting
On some platforms, CSn FTIM2.TCH is set to zero which is invalid,
an invalid hold time makes DUT timing variances, whether it works
or not on luck.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
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