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| H A D | zynqpl.c | diff c83a35f65250a8bdb519cb26680437e5c93d133d Wed Nov 27 02:03:01 CST 2013 Novasys Ingenierie <xilinx@novasys-ingenierie.com> fpga: zynq: Correct fpga load when buf is not aligned
When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is
not aligned, new_buf address became greater then buf_start address and the
load_word loop corrupts bit file data.
A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data
before buf but permits to load correctly.
Signed-off-by: Stany MARCEL <smarcel@novasys-ingenierie.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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