Searched hist:b609b7e3199912e16ef3b0447823f21fed73597e (Results 1 – 8 of 8) sorted by relevance
| /openbmc/qemu/include/hw/char/ |
| H A D | sifive_uart.h | b609b7e3199912e16ef3b0447823f21fed73597e Thu Sep 03 05:40:19 CDT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: Move sifive_uart model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|
| /openbmc/qemu/hw/char/ |
| H A D | sifive_uart.c | b609b7e3199912e16ef3b0447823f21fed73597e Thu Sep 03 05:40:19 CDT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: Move sifive_uart model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|
| H A D | Kconfig | diff b609b7e3199912e16ef3b0447823f21fed73597e Thu Sep 03 05:40:19 CDT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: Move sifive_uart model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|
| H A D | meson.build | diff b609b7e3199912e16ef3b0447823f21fed73597e Thu Sep 03 05:40:19 CDT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: Move sifive_uart model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|
| /openbmc/qemu/hw/riscv/ |
| H A D | meson.build | diff b609b7e3199912e16ef3b0447823f21fed73597e Thu Sep 03 05:40:19 CDT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: Move sifive_uart model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|
| H A D | Kconfig | diff b609b7e3199912e16ef3b0447823f21fed73597e Thu Sep 03 05:40:19 CDT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: Move sifive_uart model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|
| H A D | sifive_e.c | diff b609b7e3199912e16ef3b0447823f21fed73597e Thu Sep 03 05:40:19 CDT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: Move sifive_uart model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|
| H A D | sifive_u.c | diff b609b7e3199912e16ef3b0447823f21fed73597e Thu Sep 03 05:40:19 CDT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: Move sifive_uart model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|