Searched hist:a7240d1e4aac4cd4542d68f3cc722939550da6af (Results 1 – 2 of 2) sorted by relevance
| /openbmc/qemu/include/hw/riscv/ |
| H A D | sifive_u.h | a7240d1e4aac4cd4542d68f3cc722939550da6af Fri Mar 02 06:31:14 CST 2018 Michael Clark <mjc@sifive.com> SiFive Freedom U Series RISC-V Machine
This provides a RISC-V Board compatible with the the SiFive Freedom U SDK.
The following machine is implemented:
- 'sifive_u'; CLINT, PLIC, UART, device-tree
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
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| /openbmc/qemu/hw/riscv/ |
| H A D | sifive_u.c | a7240d1e4aac4cd4542d68f3cc722939550da6af Fri Mar 02 06:31:14 CST 2018 Michael Clark <mjc@sifive.com> SiFive Freedom U Series RISC-V Machine
This provides a RISC-V Board compatible with the the SiFive Freedom U SDK.
The following machine is implemented:
- 'sifive_u'; CLINT, PLIC, UART, device-tree
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
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