Searched hist:"8 c17cbdf8a8023abdd0009af4dc9dbc0541b4a0f" (Results 1 – 4 of 4) sorted by relevance
| /openbmc/u-boot/arch/arm/mach-omap2/am33xx/ |
| H A D | ddr.c | diff 8c17cbdf8a8023abdd0009af4dc9dbc0541b4a0f Fri Dec 09 04:29:13 CST 2016 Jyri Sarha <jsarha@ti.com> arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evm
Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
the default values LCDC suffers from DMA FIFO underflows and frame
synchronization lost errors. The initialization values are the highest
that work flawlessly when heavy memory load is generated by CPU. 32bpp
colors were used in the test. On BBB the video mode used 110MHz pixel
clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
clock.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| /openbmc/u-boot/board/ti/am335x/ |
| H A D | board.h | diff 8c17cbdf8a8023abdd0009af4dc9dbc0541b4a0f Fri Dec 09 04:29:13 CST 2016 Jyri Sarha <jsarha@ti.com> arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evm
Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
the default values LCDC suffers from DMA FIFO underflows and frame
synchronization lost errors. The initialization values are the highest
that work flawlessly when heavy memory load is generated by CPU. 32bpp
colors were used in the test. On BBB the video mode used 110MHz pixel
clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
clock.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| H A D | board.c | diff 8c17cbdf8a8023abdd0009af4dc9dbc0541b4a0f Fri Dec 09 04:29:13 CST 2016 Jyri Sarha <jsarha@ti.com> arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evm
Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
the default values LCDC suffers from DMA FIFO underflows and frame
synchronization lost errors. The initialization values are the highest
that work flawlessly when heavy memory load is generated by CPU. 32bpp
colors were used in the test. On BBB the video mode used 110MHz pixel
clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
clock.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
| /openbmc/u-boot/arch/arm/include/asm/ |
| H A D | emif.h | diff 8c17cbdf8a8023abdd0009af4dc9dbc0541b4a0f Fri Dec 09 04:29:13 CST 2016 Jyri Sarha <jsarha@ti.com> arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evm
Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
the default values LCDC suffers from DMA FIFO underflows and frame
synchronization lost errors. The initialization values are the highest
that work flawlessly when heavy memory load is generated by CPU. 32bpp
colors were used in the test. On BBB the video mode used 110MHz pixel
clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
clock.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
|