Searched hist:"834 e027a3452e1c139c5400cae550c6c5a340b28" (Results 1 – 3 of 3) sorted by relevance
| /openbmc/qemu/include/hw/riscv/ |
| H A D | sifive_u.h | diff 834e027a3452e1c139c5400cae550c6c5a340b28 Mon Aug 31 20:39:11 CDT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: sifive_u: Connect a DMA controller
SiFive FU540 SoC integrates a platform DMA controller with 4 DMA
channels. This connects the exsiting SiFive PDMA model to the SoC,
and adds its device tree data as well.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-17-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|
| /openbmc/qemu/hw/riscv/ |
| H A D | Kconfig | diff 834e027a3452e1c139c5400cae550c6c5a340b28 Mon Aug 31 20:39:11 CDT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: sifive_u: Connect a DMA controller
SiFive FU540 SoC integrates a platform DMA controller with 4 DMA
channels. This connects the exsiting SiFive PDMA model to the SoC,
and adds its device tree data as well.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-17-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|
| H A D | sifive_u.c | diff 834e027a3452e1c139c5400cae550c6c5a340b28 Mon Aug 31 20:39:11 CDT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: sifive_u: Connect a DMA controller
SiFive FU540 SoC integrates a platform DMA controller with 4 DMA
channels. This connects the exsiting SiFive PDMA model to the SoC,
and adds its device tree data as well.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-17-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|