Searched hist:"81 e94379f75c40b77d577c6bff2d7e23c9904ccf" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/qemu/include/hw/riscv/ |
| H A D | sifive_u.h | diff 81e94379f75c40b77d577c6bff2d7e23c9904ccf Fri Sep 06 11:20:18 CDT 2019 Bin Meng <bmeng.cn@gmail.com> riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet
In the past we did not have a model for PRCI, hence two handcrafted
clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the
purpose of supplying hard-coded clock frequencies. But now since we
have added the PRCI support in QEMU, we don't need them any more.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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| /openbmc/qemu/hw/riscv/ |
| H A D | sifive_u.c | diff 81e94379f75c40b77d577c6bff2d7e23c9904ccf Fri Sep 06 11:20:18 CDT 2019 Bin Meng <bmeng.cn@gmail.com> riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet
In the past we did not have a model for PRCI, hence two handcrafted
clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the
purpose of supplying hard-coded clock frequencies. But now since we
have added the PRCI support in QEMU, we don't need them any more.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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