Home
last modified time | relevance | path

Searched hist:"747778 cf69468daa1f35abb932e17032ddfe9c1a" (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/board/freescale/mx25pdk/
H A Dmx25pdk.cdiff 747778cf69468daa1f35abb932e17032ddfe9c1a Wed May 03 04:59:06 CDT 2017 Benoît Thébaudeau <benoit@wsystem.com> mx25pdk: Set the eSDHC PER clock to 48 MHz

The maximum SD clock frequency in High Speed mode is 50 MHz. This change
makes it possible to get 48 MHz from the USB PLL (240 MHz / 5 / 1)
instead of the previous 33.25 MHz from the AHB clock (133 MHz / 2 / 2).

Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>