Searched hist:"72 a9987edcedb89db988079a03c9b9c65b6ec9ac" (Results 1 – 7 of 7) sorted by relevance
| /openbmc/linux/drivers/gpu/drm/radeon/ |
| H A D | radeon_ring.c | diff 72a9987edcedb89db988079a03c9b9c65b6ec9ac Thu Jul 31 04:43:49 CDT 2014 Michel Dänzer <michel.daenzer@amd.com> drm/radeon: Always flush the HDP cache before submitting a CS to the GPU
This ensures the GPU sees all previous CPU writes to VRAM, which makes it
safe:
* For userspace to stream data from CPU to GPU via VRAM instead of GTT
* For IBs to be stored in VRAM instead of GTT
* For ring buffers to be stored in VRAM instead of GTT, if the HPD flush
is performed via MMIO
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| H A D | radeon_asic.c | diff 72a9987edcedb89db988079a03c9b9c65b6ec9ac Thu Jul 31 04:43:49 CDT 2014 Michel Dänzer <michel.daenzer@amd.com> drm/radeon: Always flush the HDP cache before submitting a CS to the GPU
This ensures the GPU sees all previous CPU writes to VRAM, which makes it
safe:
* For userspace to stream data from CPU to GPU via VRAM instead of GTT
* For IBs to be stored in VRAM instead of GTT
* For ring buffers to be stored in VRAM instead of GTT, if the HPD flush
is performed via MMIO
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| H A D | radeon_asic.h | diff 72a9987edcedb89db988079a03c9b9c65b6ec9ac Thu Jul 31 04:43:49 CDT 2014 Michel Dänzer <michel.daenzer@amd.com> drm/radeon: Always flush the HDP cache before submitting a CS to the GPU
This ensures the GPU sees all previous CPU writes to VRAM, which makes it
safe:
* For userspace to stream data from CPU to GPU via VRAM instead of GTT
* For IBs to be stored in VRAM instead of GTT
* For ring buffers to be stored in VRAM instead of GTT, if the HPD flush
is performed via MMIO
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| H A D | cik.c | diff 72a9987edcedb89db988079a03c9b9c65b6ec9ac Thu Jul 31 04:43:49 CDT 2014 Michel Dänzer <michel.daenzer@amd.com> drm/radeon: Always flush the HDP cache before submitting a CS to the GPU
This ensures the GPU sees all previous CPU writes to VRAM, which makes it
safe:
* For userspace to stream data from CPU to GPU via VRAM instead of GTT
* For IBs to be stored in VRAM instead of GTT
* For ring buffers to be stored in VRAM instead of GTT, if the HPD flush
is performed via MMIO
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| H A D | r100.c | diff 72a9987edcedb89db988079a03c9b9c65b6ec9ac Thu Jul 31 04:43:49 CDT 2014 Michel Dänzer <michel.daenzer@amd.com> drm/radeon: Always flush the HDP cache before submitting a CS to the GPU
This ensures the GPU sees all previous CPU writes to VRAM, which makes it
safe:
* For userspace to stream data from CPU to GPU via VRAM instead of GTT
* For IBs to be stored in VRAM instead of GTT
* For ring buffers to be stored in VRAM instead of GTT, if the HPD flush
is performed via MMIO
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| H A D | radeon_drv.c | diff 72a9987edcedb89db988079a03c9b9c65b6ec9ac Thu Jul 31 04:43:49 CDT 2014 Michel Dänzer <michel.daenzer@amd.com> drm/radeon: Always flush the HDP cache before submitting a CS to the GPU
This ensures the GPU sees all previous CPU writes to VRAM, which makes it
safe:
* For userspace to stream data from CPU to GPU via VRAM instead of GTT
* For IBs to be stored in VRAM instead of GTT
* For ring buffers to be stored in VRAM instead of GTT, if the HPD flush
is performed via MMIO
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| H A D | radeon.h | diff 72a9987edcedb89db988079a03c9b9c65b6ec9ac Thu Jul 31 04:43:49 CDT 2014 Michel Dänzer <michel.daenzer@amd.com> drm/radeon: Always flush the HDP cache before submitting a CS to the GPU
This ensures the GPU sees all previous CPU writes to VRAM, which makes it
safe:
* For userspace to stream data from CPU to GPU via VRAM instead of GTT
* For IBs to be stored in VRAM instead of GTT
* For ring buffers to be stored in VRAM instead of GTT, if the HPD flush
is performed via MMIO
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|