Searched hist:"5 d176f751ee3c6eededd984ad409bff201f436a7" (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | processor.h | diff 5d176f751ee3c6eededd984ad409bff201f436a7 Wed Sep 14 03:02:16 CDT 2016 Cyril Bur <cyrilbur@gmail.com> powerpc: tm: Enable transactional memory (TM) lazily for userspace
Currently the MSR TM bit is always set if the hardware is TM capable.
This adds extra overhead as it means the TM SPRS (TFHAR, TEXASR and
TFAIR) must be swapped for each process regardless of if they use TM.
For processes that don't use TM the TM MSR bit can be turned off
allowing the kernel to avoid the expensive swap of the TM registers.
A TM unavailable exception will occur if a thread does use TM and the
kernel will enable MSR_TM and leave it so for some time afterwards.
Signed-off-by: Cyril Bur <cyrilbur@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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| /openbmc/linux/arch/powerpc/kernel/ |
| H A D | traps.c | diff 5d176f751ee3c6eededd984ad409bff201f436a7 Wed Sep 14 03:02:16 CDT 2016 Cyril Bur <cyrilbur@gmail.com> powerpc: tm: Enable transactional memory (TM) lazily for userspace
Currently the MSR TM bit is always set if the hardware is TM capable.
This adds extra overhead as it means the TM SPRS (TFHAR, TEXASR and
TFAIR) must be swapped for each process regardless of if they use TM.
For processes that don't use TM the TM MSR bit can be turned off
allowing the kernel to avoid the expensive swap of the TM registers.
A TM unavailable exception will occur if a thread does use TM and the
kernel will enable MSR_TM and leave it so for some time afterwards.
Signed-off-by: Cyril Bur <cyrilbur@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
|
| H A D | process.c | diff 5d176f751ee3c6eededd984ad409bff201f436a7 Wed Sep 14 03:02:16 CDT 2016 Cyril Bur <cyrilbur@gmail.com> powerpc: tm: Enable transactional memory (TM) lazily for userspace
Currently the MSR TM bit is always set if the hardware is TM capable.
This adds extra overhead as it means the TM SPRS (TFHAR, TEXASR and
TFAIR) must be swapped for each process regardless of if they use TM.
For processes that don't use TM the TM MSR bit can be turned off
allowing the kernel to avoid the expensive swap of the TM registers.
A TM unavailable exception will occur if a thread does use TM and the
kernel will enable MSR_TM and leave it so for some time afterwards.
Signed-off-by: Cyril Bur <cyrilbur@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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