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| /openbmc/linux/drivers/net/ethernet/xilinx/ |
| H A D | xilinx_axienet.h | diff 4e958f33ee8f404787711416fe0f78cce2b2f4e2 Tue Mar 24 08:23:45 CDT 2020 Andre Przywara <andre.przywara@arm.com> net: axienet: Upgrade descriptors to hold 64-bit addresses
Newer revisions of the AXI DMA IP (>= v7.1) support 64-bit addresses,
both for the descriptors itself, as well as for the buffers they are
pointing to.
This is realised by adding "MSB" words for the next and phys pointer
right behind the existing address word, now named "LSB". These MSB words
live in formerly reserved areas of the descriptor.
If the hardware supports it, write both words when setting an address.
The buffer address is handled by two wrapper functions, the two
occasions where we set the next pointers are open coded.
For now this is guarded by a flag which we don't set yet.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| H A D | xilinx_axienet_main.c | diff 4e958f33ee8f404787711416fe0f78cce2b2f4e2 Tue Mar 24 08:23:45 CDT 2020 Andre Przywara <andre.przywara@arm.com> net: axienet: Upgrade descriptors to hold 64-bit addresses
Newer revisions of the AXI DMA IP (>= v7.1) support 64-bit addresses,
both for the descriptors itself, as well as for the buffers they are
pointing to.
This is realised by adding "MSB" words for the next and phys pointer
right behind the existing address word, now named "LSB". These MSB words
live in formerly reserved areas of the descriptor.
If the hardware supports it, write both words when setting an address.
The buffer address is handled by two wrapper functions, the two
occasions where we set the next pointers are open coded.
For now this is guarded by a flag which we don't set yet.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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