Searched hist:"2958 d17a898416c6193431676f6130b68a2cb9fc" (Results 1 – 10 of 10) sorted by relevance
| /openbmc/linux/drivers/net/ethernet/marvell/octeontx2/nic/ |
| H A D | otx2_struct.h | diff 2958d17a898416c6193431676f6130b68a2cb9fc Sat Sep 10 02:54:14 CDT 2022 Hariprasad Kelam <hkelam@marvell.com> octeontx2-pf: Add support for ptp 1-step mode on CN10K silicon
Add support for ptp 1-step mode using timecounter. The seconds and
nanoseconds to be updated in PTP header are calculated by adding the
timecounter offset to the free running PTP clock counter time. The PF
driver periodically gets the PTP clock time using AF mbox. The 1-step
support uses HW feature to update correction field rather than
OriginTimestamp field in PTP header.
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | otx2_ptp.c | diff 2958d17a898416c6193431676f6130b68a2cb9fc Sat Sep 10 02:54:14 CDT 2022 Hariprasad Kelam <hkelam@marvell.com> octeontx2-pf: Add support for ptp 1-step mode on CN10K silicon
Add support for ptp 1-step mode using timecounter. The seconds and
nanoseconds to be updated in PTP header are calculated by adding the
timecounter offset to the free running PTP clock counter time. The PF
driver periodically gets the PTP clock time using AF mbox. The 1-step
support uses HW feature to update correction field rather than
OriginTimestamp field in PTP header.
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | otx2_txrx.c | diff 2958d17a898416c6193431676f6130b68a2cb9fc Sat Sep 10 02:54:14 CDT 2022 Hariprasad Kelam <hkelam@marvell.com> octeontx2-pf: Add support for ptp 1-step mode on CN10K silicon
Add support for ptp 1-step mode using timecounter. The seconds and
nanoseconds to be updated in PTP header are calculated by adding the
timecounter offset to the free running PTP clock counter time. The PF
driver periodically gets the PTP clock time using AF mbox. The 1-step
support uses HW feature to update correction field rather than
OriginTimestamp field in PTP header.
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | otx2_ethtool.c | diff 2958d17a898416c6193431676f6130b68a2cb9fc Sat Sep 10 02:54:14 CDT 2022 Hariprasad Kelam <hkelam@marvell.com> octeontx2-pf: Add support for ptp 1-step mode on CN10K silicon
Add support for ptp 1-step mode using timecounter. The seconds and
nanoseconds to be updated in PTP header are calculated by adding the
timecounter offset to the free running PTP clock counter time. The PF
driver periodically gets the PTP clock time using AF mbox. The 1-step
support uses HW feature to update correction field rather than
OriginTimestamp field in PTP header.
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | otx2_common.h | diff 2958d17a898416c6193431676f6130b68a2cb9fc Sat Sep 10 02:54:14 CDT 2022 Hariprasad Kelam <hkelam@marvell.com> octeontx2-pf: Add support for ptp 1-step mode on CN10K silicon
Add support for ptp 1-step mode using timecounter. The seconds and
nanoseconds to be updated in PTP header are calculated by adding the
timecounter offset to the free running PTP clock counter time. The PF
driver periodically gets the PTP clock time using AF mbox. The 1-step
support uses HW feature to update correction field rather than
OriginTimestamp field in PTP header.
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | otx2_pf.c | diff 2958d17a898416c6193431676f6130b68a2cb9fc Sat Sep 10 02:54:14 CDT 2022 Hariprasad Kelam <hkelam@marvell.com> octeontx2-pf: Add support for ptp 1-step mode on CN10K silicon
Add support for ptp 1-step mode using timecounter. The seconds and
nanoseconds to be updated in PTP header are calculated by adding the
timecounter offset to the free running PTP clock counter time. The PF
driver periodically gets the PTP clock time using AF mbox. The 1-step
support uses HW feature to update correction field rather than
OriginTimestamp field in PTP header.
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| /openbmc/linux/drivers/net/ethernet/marvell/octeontx2/af/ |
| H A D | rpm.h | diff 2958d17a898416c6193431676f6130b68a2cb9fc Sat Sep 10 02:54:14 CDT 2022 Hariprasad Kelam <hkelam@marvell.com> octeontx2-pf: Add support for ptp 1-step mode on CN10K silicon
Add support for ptp 1-step mode using timecounter. The seconds and
nanoseconds to be updated in PTP header are calculated by adding the
timecounter offset to the free running PTP clock counter time. The PF
driver periodically gets the PTP clock time using AF mbox. The 1-step
support uses HW feature to update correction field rather than
OriginTimestamp field in PTP header.
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | rpm.c | diff 2958d17a898416c6193431676f6130b68a2cb9fc Sat Sep 10 02:54:14 CDT 2022 Hariprasad Kelam <hkelam@marvell.com> octeontx2-pf: Add support for ptp 1-step mode on CN10K silicon
Add support for ptp 1-step mode using timecounter. The seconds and
nanoseconds to be updated in PTP header are calculated by adding the
timecounter offset to the free running PTP clock counter time. The PF
driver periodically gets the PTP clock time using AF mbox. The 1-step
support uses HW feature to update correction field rather than
OriginTimestamp field in PTP header.
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | rvu_reg.h | diff 2958d17a898416c6193431676f6130b68a2cb9fc Sat Sep 10 02:54:14 CDT 2022 Hariprasad Kelam <hkelam@marvell.com> octeontx2-pf: Add support for ptp 1-step mode on CN10K silicon
Add support for ptp 1-step mode using timecounter. The seconds and
nanoseconds to be updated in PTP header are calculated by adding the
timecounter offset to the free running PTP clock counter time. The PF
driver periodically gets the PTP clock time using AF mbox. The 1-step
support uses HW feature to update correction field rather than
OriginTimestamp field in PTP header.
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | rvu_nix.c | diff 2958d17a898416c6193431676f6130b68a2cb9fc Sat Sep 10 02:54:14 CDT 2022 Hariprasad Kelam <hkelam@marvell.com> octeontx2-pf: Add support for ptp 1-step mode on CN10K silicon
Add support for ptp 1-step mode using timecounter. The seconds and
nanoseconds to be updated in PTP header are calculated by adding the
timecounter offset to the free running PTP clock counter time. The PF
driver periodically gets the PTP clock time using AF mbox. The 1-step
support uses HW feature to update correction field rather than
OriginTimestamp field in PTP header.
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com>
Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|