Searched hist:"2308092 b2b78e6e083092bd3599cec6a0769319e" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/qemu/include/hw/riscv/ |
| H A D | sifive_u.h | diff 2308092b2b78e6e083092bd3599cec6a0769319e Thu Apr 26 13:15:24 CDT 2018 Alistair Francis <alistair.francis@wdc.com> hw/riscv/sifive_u: Create a SiFive U SoC object
Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine.
We leave the SoC, RAM, device tree and reset/fdt loading as part of the
machine. All the other device creation has been moved to the SoC.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
|
| /openbmc/qemu/hw/riscv/ |
| H A D | sifive_u.c | diff 2308092b2b78e6e083092bd3599cec6a0769319e Thu Apr 26 13:15:24 CDT 2018 Alistair Francis <alistair.francis@wdc.com> hw/riscv/sifive_u: Create a SiFive U SoC object
Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine.
We leave the SoC, RAM, device tree and reset/fdt loading as part of the
machine. All the other device creation has been moved to the SoC.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
|