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/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dlinux,wdt-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/linux,wdt-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO-controlled Watchdog
10 - Guenter Roeck <linux@roeck-us.net>
11 - Robert Marko <robert.marko@sartura.hr>
15 const: linux,wdt-gpio
18 description: gpio connection to WDT reset pin
24 - description:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt7620-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7620-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
20 const: ralink,mt7620-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
31 $ref: pinmux-node.yaml#
[all …]
H A Dmediatek,mt7621-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7621-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
20 const: ralink,mt7621-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
31 $ref: pinmux-node.yaml#
[all …]
H A Dmediatek,mt76x8-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt76x8-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
20 const: ralink,mt76x8-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
31 $ref: pinmux-node.yaml#
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dbrcm,bcm3380.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm3380-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/reset/bcm3380-reset.h>
20 #address-cells = <1>;
21 #size-cells = <0>;
22 u-boot,dm-pre-reloc;
25 compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
28 u-boot,dm-pre-reloc;
32 compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
[all …]
H A Dbrcm,bcm6338.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm6338-clock.h>
7 #include <dt-bindings/dma/bcm6338-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/bcm6338-reset.h>
21 #address-cells = <1>;
22 #size-cells = <0>;
23 u-boot,dm-pre-reloc;
26 compatible = "brcm,bcm6338-cpu", "mips,mips4Kc";
29 u-boot,dm-pre-reloc;
[all …]
H A Dbrcm,bcm6348.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm6348-clock.h>
7 #include <dt-bindings/dma/bcm6348-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/bcm6348-reset.h>
21 #address-cells = <1>;
22 #size-cells = <0>;
23 u-boot,dm-pre-reloc;
26 compatible = "brcm,bcm6348-cpu", "mips,mips4Kc";
29 u-boot,dm-pre-reloc;
[all …]
H A Dbrcm,bcm6318.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm6318-clock.h>
7 #include <dt-bindings/dma/bcm6318-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/power-domain/bcm6318-power-domain.h>
10 #include <dt-bindings/reset/bcm6318-reset.h>
22 #address-cells = <1>;
23 #size-cells = <0>;
24 u-boot,dm-pre-reloc;
27 compatible = "brcm,bcm6318-cpu", "mips,mips4Kc";
[all …]
H A Dbrcm,bcm6368.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm6368-clock.h>
7 #include <dt-bindings/dma/bcm6368-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/bcm6368-reset.h>
21 #address-cells = <1>;
22 #size-cells = <0>;
23 u-boot,dm-pre-reloc;
26 compatible = "brcm,bcm6368-cpu", "mips,mips4Kc";
29 u-boot,dm-pre-reloc;
[all …]
H A Dbrcm,bcm6362.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm6362-clock.h>
7 #include <dt-bindings/dma/bcm6362-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/power-domain/bcm6362-power-domain.h>
10 #include <dt-bindings/reset/bcm6362-reset.h>
23 #address-cells = <1>;
24 #size-cells = <0>;
25 u-boot,dm-pre-reloc;
28 compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
[all …]
H A Dbrcm,bcm6358.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm6358-clock.h>
7 #include <dt-bindings/dma/bcm6358-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/bcm6358-reset.h>
21 #address-cells = <1>;
22 #size-cells = <0>;
23 u-boot,dm-pre-reloc;
26 compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
29 u-boot,dm-pre-reloc;
[all …]
H A Dbrcm,bcm6328.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm6328-clock.h>
7 #include <dt-bindings/dma/bcm6328-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/power-domain/bcm6328-power-domain.h>
10 #include <dt-bindings/reset/bcm6328-reset.h>
22 #address-cells = <1>;
23 #size-cells = <0>;
24 u-boot,dm-pre-reloc;
27 compatible = "brcm,bcm6328-cpu", "mips,mips4Kc";
[all …]
H A Dbrcm,bcm63268.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/bcm63268-clock.h>
7 #include <dt-bindings/dma/bcm63268-dma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/power-domain/bcm63268-power-domain.h>
10 #include <dt-bindings/reset/bcm63268-reset.h>
23 #address-cells = <1>;
24 #size-cells = <0>;
25 u-boot,dm-pre-reloc;
28 compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
[all …]
H A Dmt7628a.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #address-cells = <1>;
5 #size-cells = <1>;
6 compatible = "ralink,mt7628a-soc";
9 #address-cells = <1>;
10 #size-cells = <0>;
19 resetc: reset-controller {
20 compatible = "ralink,rt2880-reset";
21 #reset-cells = <1>;
24 cpuintc: interrupt-controller {
[all …]
/openbmc/linux/arch/powerpc/platforms/52xx/
H A Dmpc52xx_gpt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * for GPIO or can be used to raise interrupts. The timer function can
14 * This driver supports the GPIO and IRQ controller functions of the GPT
17 * The timer gpt0 can be used as watchdog (wdt). If the wdt mode is used,
19 * -EBUSY). Thus, the safety wdt function always has precedence over the gpt
21 * this means that gpt0 is locked in wdt mode until the next reboot - this
24 * To use the GPIO function, the following two properties must be added
27 * gpio-controller;
28 * #gpio-cells = < 2 >;
29 * This driver will register the GPIO pin if it finds the gpio-controller
[all …]
H A Dmpc52xx_common.c15 #include <linux/gpio.h>
27 { .compatible = "fsl,mpc5200-xlb", },
28 { .compatible = "mpc5200-xlb", },
32 { .compatible = "fsl,mpc5200-immr", },
33 { .compatible = "fsl,mpc5200b-immr", },
34 { .compatible = "simple-bus", },
73 out_be32(&xlb->master_pri_enable, 0xff); in mpc5200_setup_xlb_arbiter()
74 out_be32(&xlb->master_priority, 0x11111111); in mpc5200_setup_xlb_arbiter()
79 * transaction and re-enable it afterwards ...) in mpc5200_setup_xlb_arbiter()
83 out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_PLDIS); in mpc5200_setup_xlb_arbiter()
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dgef_ppc9a.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
17 /include/ "mpc8641si-pre.dtsi"
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
42 compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
44 bank-width = <4>;
45 device-width = <2>;
46 #address-cells = <1>;
47 #size-cells = <1>;
[all …]
H A Dge_imp3a.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
11 /include/ "p2020si-pre.dtsi"
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
39 bank-width = <2>;
40 device-width = <1>;
45 read-only;
51 #address-cells = <1>;
[all …]
H A Dgef_sbc310.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
17 /include/ "mpc8641si-pre.dtsi"
39 compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
41 bank-width = <2>;
42 device-width = <2>;
43 #address-cells = <1>;
44 #size-cells = <1>;
48 read-only;
54 compatible = "gef,sbc310-paged-flash", "cfi-flash";
[all …]
H A Dgef_sbc610.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
17 /include/ "mpc8641si-pre.dtsi"
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
42 compatible = "gef,sbc610-firmware-mirror", "cfi-flash";
44 bank-width = <4>;
45 device-width = <2>;
46 #address-cells = <1>;
47 #size-cells = <1>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dkontron,sl28cpld.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Walle <michael@walle.cc>
15 GPIO controller.
26 "#address-cells":
29 "#size-cells":
32 "#interrupt-cells":
38 interrupt-controller: true
41 "^gpio(@[0-9a-f]+)?$":
[all …]
/openbmc/linux/arch/arm/boot/dts/synaptics/
H A Dberlin2cd.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Marvell Armada 1500-mini (BG2CD) SoC";
17 #address-cells = <1>;
18 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a9";
[all …]
/openbmc/linux/arch/mips/boot/dts/qca/
H A Dar9132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ath79-clk.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
22 cpuintc: interrupt-controller {
23 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
25 interrupt-controller;
26 #interrupt-cells = <1>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dkeystone.dtsi9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/gpio/gpio.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
18 interrupt-parent = <&gic>;
31 stdout-path = &uart0;
38 gic: interrupt-controller {
39 compatible = "arm,cortex-a15-gic";
40 #interrupt-cells = <3>;
41 interrupt-controller;
[all …]
/openbmc/u-boot/board/ve8313/
H A Dve8313.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
40 out_be32(&im->sysconf.ddrlaw[0].bar, in fixed_sdram()
42 out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1))); in fixed_sdram()
43 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); in fixed_sdram()
54 out_be32(&im->ddr.csbnds[0].csbnds, in fixed_sdram()
56 (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & in fixed_sdram()
58 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
61 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
63 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); in fixed_sdram()
[all …]

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