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/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20-tamonten.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 stdout-path = "serial0:115200n8";
24 vdd-supply = <&hdmi_vdd_reg>;
25 pll-supply = <&hdmi_pll_reg>;
27 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
28 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
34 pinctrl-names = "default";
35 pinctrl-0 = <&state_default>;
137 "lvs";
242 "lvs", "pmc";
[all …]
H A Dtegra20-paz00.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
8 #include "tegra20-cpu-opp.dtsi"
9 #include "tegra20-cpu-opp-microvolt.dtsi"
25 stdout-path = "serial0:115200n8";
44 vdd-supply = <&hdmi_vdd_reg>;
45 pll-supply = <&hdmi_pll_reg>;
47 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
[all …]
H A Dtegra20-harmony.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
37 hdmi-supply = <&vdd_5v0_hdmi>;
38 vdd-supply = <&hdmi_vdd_reg>;
39 pll-supply = <&hdmi_pll_reg>;
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
48 pinctrl-names = "default";
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H A Dtegra20-ventana.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
7 #include "tegra20-cpu-opp.dtsi"
8 #include "tegra20-cpu-opp-microvolt.dtsi"
21 stdout-path = "serial0:115200n8";
40 vdd-supply = <&hdmi_vdd_reg>;
41 pll-supply = <&hdmi_pll_reg>;
43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
[all …]
H A Dtegra20-seaboard.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
37 vdd-supply = <&hdmi_vdd_reg>;
38 pll-supply = <&hdmi_pll_reg>;
39 hdmi-supply = <&vdd_hdmi>;
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
48 pinctrl-names = "default";
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H A Dtegra20-asus-tf101.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
16 chassis-type = "convertible";
33 * pre-existing /chosen node to be available to insert the
[all …]
H A Dtegra20-acer-a500-picasso.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
32 * pre-existing /chosen node to be available to insert the
41 reserved-memory {
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H A Dtegra20-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A;
7 * Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A;
8 * Colibri T20 512MB IT V1.2A
22 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
23 nvidia,hpd-gpio =
25 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
26 vdd-supply = <&reg_3v3_avdd_hdmi>;
31 lan-reset-n-hog {
32 gpio-hog;
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/openbmc/u-boot/arch/arm/dts/
H A Dtegra20-tamonten.dtsi13 vdd-supply = <&hdmi_vdd_reg>;
14 pll-supply = <&hdmi_pll_reg>;
16 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
17 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
23 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>;
126 "lvs";
189 nvidia,pull = <1>;
190 nvidia,tristate = <1>;
198 nvidia,tristate = <1>;
[all …]
H A Dtegra20-paz00.dts1 /dts-v1/;
3 #include <dt-bindings/input/input.h>
11 stdout-path = &uarta;
39 display-timings {
42 clock-frequency = <54030000>;
45 hback-porch = <160>;
46 hfront-porch = <24>;
47 hsync-len = <136>;
48 vback-porch = <3>;
49 vfront-porch = <61>;
[all …]
H A Dtegra20-ventana.dts1 /dts-v1/;
3 #include <dt-bindings/input/input.h>
11 stdout-path = &uartd;
38 display-timings {
41 clock-frequency = <70600000>;
44 hback-porch = <58>;
45 hfront-porch = <58>;
46 hsync-len = <58>;
47 vback-porch = <4>;
48 vfront-porch = <4>;
[all …]
H A Dtegra20-harmony.dts1 /dts-v1/;
3 #include <dt-bindings/input/input.h>
11 stdout-path = &uartd;
38 display-timings {
41 clock-frequency = <42430000>;
44 hback-porch = <138>;
45 hfront-porch = <34>;
46 hsync-len = <136>;
47 vback-porch = <21>;
48 vfront-porch = <4>;
[all …]
H A Dtegra20-seaboard.dts1 /dts-v1/;
3 #include <dt-bindings/input/input.h>
31 stdout-path = &uartd;
47 display-timings {
50 clock-frequency = <70600000>;
53 hback-porch = <58>;
54 hfront-porch = <58>;
55 hsync-len = <58>;
56 vback-porch = <4>;
57 vfront-porch = <4>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsdm845-db845c.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
11 #include <dt-bindings/sound/qcom,q6afe.h>
12 #include <dt-bindings/sound/qcom,q6asm.h>
14 #include "sdm845-wcd9340.dtsi"
21 qcom,msm-id = <341 0x20001>;
22 qcom,board-id = <8 0>;
[all …]
H A Dsdm845-samsung-starqltechn.dts1 // SPDX-License-Identifier: GPL-2.0
3 * SDM845 Samsung S9 (SM-G9600) (starqltechn / star2qltechn) common device tree source
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
15 chassis-type = "handset";
16 model = "Samsung Galaxy S9 SM-G9600";
20 #address-cells = <2>;
21 #size-cells = <2>;
24 compatible = "simple-framebuffer";
[all …]
H A Dsdm845-lg-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
16 /delete-node/ &adsp_mem;
17 /delete-node/ &cdsp_mem;
18 /delete-node/ &gpu_mem;
19 /delete-node/ &ipa_fw_mem;
20 /delete-node/ &mba_region;
21 /delete-node/ &mpss_region;
[all …]
H A Dsdm845-mtp.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
17 compatible = "qcom,sdm845-mtp", "qcom,sdm845";
18 chassis-type = "handset";
25 stdout-path = "serial0:115200n8";
28 vph_pwr: vph-pwr-regulator {
29 compatible = "regulator-fixed";
30 regulator-name = "vph_pwr";
31 regulator-min-microvolt = <3700000>;
[all …]
H A Dsdm845-shift-axolotl.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
20 qcom,msm-id = <321 0x20001>;
21 qcom,board-id = <11 0>;
30 #address-cells = <2>;
31 #size-cells = <2>;
34 stdout-path = "serial0";
[all …]
H A Dsdm845-sony-xperia-tama.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
15 qcom,msm-id = <321 0x20001>; /* SDM845 v2.1 */
16 qcom,board-id = <8 0>;
24 stdout-path = "serial0:115200n8";
27 gpio-keys {
28 compatible = "gpio-keys";
30 pinctrl-0 = <&focus_n &snapshot_n &vol_down_n &vol_up_n>;
[all …]
H A Dsdm845-oneplus-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/input/linux-event-codes.h>
11 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
12 #include <dt-bindings/sound/qcom,q6afe.h>
13 #include <dt-bindings/sound/qcom,q6asm.h>
16 #include "sdm845-wcd9340.dtsi"
20 /delete-node/ &rmtfs_mem;
29 stdout-path = "serial0:115200n8";
32 gpio-hall-sensor {
[all …]
H A Dsdm845-cheza.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
25 stdout-path = "serial0:115200n8";
29 compatible = "pwm-backlight";
31 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
32 power-supply = <&ppvar_sys>;
33 pinctrl-names = "default";
34 pinctrl-0 = <&ap_edp_bklten>;
37 /* FIXED REGULATORS - parents above children */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dqcom,rpmh-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/qcom,rpmh-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
14 rpmh-regulator devices support PMIC regulator management via the Voltage
22 It is used for clock buffers, low-voltage switches, and LDO/SMPS regulators
37 For PM6150, smps1 - smps5, ldo1 - ldo19
38 For PM6150L, smps1 - smps8, ldo1 - ldo11, bob
[all …]
/openbmc/linux/drivers/regulator/
H A Dqcom-rpmh-regulator.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
17 #include <soc/qcom/cmd-db.h>
20 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
23 * enum rpmh_regulator_type - supported RPMh accelerator types
48 #define PMIC4_BOB_MODE_PFM 1
49 #define PMIC4_BOB_MODE_AUTO 2
61 #define PMIC5_BOB_MODE_PASS 2
67 * struct rpmh_vreg_hw_data - RPMh regulator hardware configurations
96 * struct rpmh_vreg - individual RPMh regulator data structure encapsulating a
[all …]
/openbmc/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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