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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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H A Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234-p3767.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 vcc-supply = <&vdd_1v8_hs>;
18 address-width = <8>;
21 read-only;
29 compatible = "jedec,spi-nor";
31 spi-max-frequency = <102000000>;
32 spi-tx-bus-width = <4>;
33 spi-rx-bus-width = <4>;
44 bus-width = <4>;
45 cd-gpios = <&gpio TEGRA234_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>;
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H A Dtegra234-p3740-0002.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/sound/rt5640.h>
6 compatible = "nvidia,p3740-0002";
15 dai-format = "i2s";
16 remote-endpoint = <&rt5640_ep>;
26 bitclock-master;
27 frame-master;
36 rt5640: audio-codec@1c {
39 interrupt-parent = <&gpio>;
42 clock-names = "mclk";
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H A Dtegra234-p3701-0000.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "tegra234-p3701.dtsi"
8 compatible = "nvidia,p3701-0000", "nvidia,tegra234";
19 vcc-supply = <&vdd_1v8_hs>;
20 address-width = <8>;
23 read-only;
31 compatible = "jedec,spi-nor";
33 spi-max-frequency = <102000000>;
34 spi-tx-bus-width = <4>;
35 spi-rx-bus-width = <4>;
[all …]
H A Dtegra194-p3668.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/mfd/max77620.h>
24 stdout-path = "serial0:115200n8";
31 phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(R, 1) GPIO_ACTIVE_LOW>;
32 phy-handle = <&phy>;
33 phy-mode = "rgmii-id";
36 #address-cells = <1>;
37 #size-cells = <0>;
39 phy: ethernet-phy@0 {
40 compatible = "ethernet-phy-ieee802.3-c22";
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H A Dtegra194-p2888.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/mfd/max77620.h>
27 stdout-path = "serial0:115200n8";
34 phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>;
35 phy-handle = <&phy>;
36 phy-mode = "rgmii-id";
39 #address-cells = <1>;
40 #size-cells = <0>;
42 phy: ethernet-phy@0 {
43 compatible = "ethernet-phy-ieee802.3-c22";
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H A Dtegra186-p3509-0000+p3636-0001.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/mfd/max77620.h>
12 compatible = "nvidia,p3509-0000+p3636-0001", "nvidia,tegra186";
30 stdout-path = "serial0:115200n8";
41 phy-reset-gpios = <&gpio_aon TEGRA186_AON_GPIO(AA, 6) GPIO_ACTIVE_LOW>;
42 phy-handle = <&phy>;
43 phy-mode = "rgmii-id";
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H A Dtegra186-p2771-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra186-p3310.dtsi"
11 compatible = "nvidia,p2771-0000", "nvidia,tegra186";
23 #address-cells = <1>;
24 #size-cells = <0>;
30 remote-endpoint = <&xbar_i2s1_ep>;
38 dai-format = "i2s";
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/openbmc/linux/drivers/power/supply/
H A Dbq25890_charger.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #include <linux/usb/phy.h>
93 u8 vclamp; /* IBAT compensation voltage limit */ member
113 char name[28]; /* "bq25890-charger-%d" */
272 * Most of the val -> idx conversions can be computed, given the minimum,
322 0, -10, -20, -30, -40, -60, -70, -80,
323 -90, -10, -120, -140, -150, -170, -190, -210,
367 ret = regmap_field_read(bq->rmap_fields[field_id], &val); in bq25890_field_read()
377 return regmap_field_write(bq->rmap_fields[field_id], val); in bq25890_field_write()
394 rtbl_size = (rtbl->max - rtbl->min) / rtbl->step + 1; in bq25890_find_idx()
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H A Dbq24190_charger.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/extcon-provider.h>
32 #define BQ24190_REG_POC 0x01 /* Power-On Configuration */
57 #define BQ24190_REG_PCTCC 0x03 /* Pre-charge/Termination Current Cntl */
190 * The tables below provide a 2-way mapping for the value that goes in
191 * the register field and the real-world value that it represents.
193 * number at that index in the array is the real-world value that it
233 * 'val'. The index range returned is 0 to 'tbl_size' - 1. Assumes that
245 return i - 1; in bq24190_find_idx()
254 ret = i2c_smbus_read_byte_data(bdi->client, reg); in bq24190_read()
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/openbmc/linux/drivers/phy/tegra/
H A Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
280 writel(value, priv->ao_regs + offset); in ao_writel()
285 return readl(priv->ao_regs + offset); in ao_readl()
294 /* USB 2.0 UTMI PHY support */
304 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
306 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
307 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
308 usb2->base.index = index; in tegra186_usb2_lane_probe()
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