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/openbmc/linux/tools/testing/selftests/timers/
H A Dadjtick.c7 * $ gcc adjtick.c -o adjtick -lrt
39 if (val < 0) in llabs()
40 val = -val; in llabs()
66 return end_ns - start_ns; in diff_timespec()
72 long long diff = 0, tmp; in get_monotonic_and_raw()
79 for (i = 0; i < 3; i++) { in get_monotonic_and_raw()
87 if (diff == 0 || newdiff < diff) { in get_monotonic_and_raw()
110 eppm = (delta1*MILLION)/delta2 - MILLION; in get_ppm_drift()
118 struct timex tx1; in check_tick_adj() local
120 tx1.modes = ADJ_TICK; in check_tick_adj()
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H A Draw_skew.c9 * $ gcc raw_skew.c -o raw_skew -lrt
36 __x < 0 ? -(-__x >> __s) : __x >> __s; \
41 if (val < 0) in llabs()
42 val = -val; in llabs()
66 return end_ns - start_ns; in diff_timespec()
72 long long diff = 0, tmp; in get_monotonic_and_raw()
75 for (i = 0; i < 3; i++) { in get_monotonic_and_raw()
83 if (diff == 0 || newdiff < diff) { in get_monotonic_and_raw()
96 struct timex tx1, tx2; in main() local
102 return -1; in main()
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/openbmc/linux/sound/soc/tegra/
H A Dtegra210_ahub.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra210_ahub.c - Tegra210 AHUB driver
5 // Copyright (c) 2020-2024, NVIDIA CORPORATION. All rights reserved.
22 struct soc_enum *e = (struct soc_enum *)kctl->private_value; in tegra_ahub_get_value_enum()
23 unsigned int reg, i, bit_pos = 0; in tegra_ahub_get_value_enum()
27 * If nothing is set, position would be 0 and it corresponds to 'None'. in tegra_ahub_get_value_enum()
29 for (i = 0; i < ahub->soc_data->reg_count; i++) { in tegra_ahub_get_value_enum()
32 reg = e->reg + (TEGRA210_XBAR_PART1_RX * i); in tegra_ahub_get_value_enum()
34 reg_val &= ahub->soc_data->mask[i]; in tegra_ahub_get_value_enum()
38 (8 * cmpnt->val_bytes * i); in tegra_ahub_get_value_enum()
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dti,icssg-prueth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,icssg-prueth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Md Danish Anwar <danishanwar@ti.com>
13 Ethernet based on the Programmable Real-Time Unit and Industrial
17 - $ref: /schemas/remoteproc/ti,pru-consumer.yaml#
22 - ti,am654-icssg-prueth # for AM65x SoC family
32 dma-names:
34 - const: tx0-0
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/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-edp.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
22 #include <dt-bindings/phy/phy.h>
24 #include "phy-qcom-qmp.h"
27 #define DP_PHY_CFG 0x0010
28 #define DP_PHY_CFG_1 0x0014
29 #define DP_PHY_PD_CTL 0x001c
30 #define DP_PHY_MODE 0x0020
32 #define DP_PHY_AUX_CFG0 0x0024
33 #define DP_PHY_AUX_CFG1 0x0028
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/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - enum:
20 - renesas,r9a06g032-sja1000 # RZ/N1D
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/openbmc/qemu/target/riscv/
H A Dvector_internals.h2 * RISC-V Vector Extension Internals
4 * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
25 #include "tcg/tcg-gvec-desc.h"
29 if (env->vstart >= vl) { \
30 env->vstart = 0; \
33 } while (0)
41 * Note that vector data is stored in host-endian 64-bit chunks,
42 * so addressing units smaller than that needs a host-endian fixup.
63 * 1 000 0
67 * - 100 -
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/openbmc/linux/Documentation/devicetree/bindings/firmware/
H A Dfsl,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
31 $ref: /schemas/clock/fsl,scu-clk.yaml
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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-vpu.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 #address-cells = <1>;
9 #size-cells = <1>;
10 ranges = <0x2c000000 0x0 0x2c000000 0x2000000>;
11 reg = <0 0x2c000000 0 0x1000000>;
12 power-domains = <&pd IMX_SC_R_VPU>;
16 compatible = "fsl,imx6sx-mu";
17 reg = <0x2d000000 0x20000>;
19 #mbox-cells = <2>;
20 power-domains = <&pd IMX_SC_R_VPU_MU_0>;
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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Damphion,vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ming Qian <ming.qian@nxp.com>
12 - Shijie Qin <shijie.qin@nxp.com>
14 description: |-
20 pattern: "^vpu@[0-9a-f]+$"
24 - enum:
25 - nxp,imx8qm-vpu
26 - nxp,imx8qxp-vpu
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/openbmc/linux/Documentation/driver-api/dmaengine/
H A Dpxa_dma.rst2 PXA/MMP - DMA Slave controller
21 This implies that even if an irq/tasklet is triggered by end of tx1, but
22 at the time of irq/dma tx2 is already finished, tx1->complete() and
23 tx2->complete() should be called.
36 A driver should be able to request a priority, especially the real-time
46 b) Transfer anatomy for a scatter-gather transfer
50 +------------+-----+---------------+----------------+-----------------+
51 | desc-sg[0] | ... | desc-sg[last] | status updater | finisher/linker |
52 +------------+-----+---------------+----------------+-----------------+
54 This structure is pointed by dma->sg_cpu.
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/openbmc/linux/drivers/net/ethernet/8390/
H A Dlib8390.c1 // SPDX-License-Identifier: GPL-1.0+
5 Written 1992-94 by Donald Becker.
16 This is the chip-specific code for many 8390-based ethernet adaptors.
17 This is not a complete driver, it must be combined with board-specific
23 you have found something that needs changing. -- PG
39 Paul Gortmaker : add kmod support for auto-loading of the 8390
79 /* These are the operational function interfaces to board-specific
88 "page" value uses the 8390's 256-byte pages.
97 #define ei_reset_8390 (ei_local->reset_8390)
98 #define ei_block_output (ei_local->block_output)
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H A Daxnet_cs.c1 // SPDX-License-Identifier: GPL-1.0+
5 A PCMCIA ethernet driver for Asix AX88190-based cards
7 The Asix AX88190 is a NS8390-derived chipset with a few nasty
14 Copyright (C) 2001 David A. Hinds -- dahinds@users.sourceforge.net
51 #define AXNET_CMD 0x00
52 #define AXNET_DATAPORT 0x10 /* NatSemi-defined port window offset. */
53 #define AXNET_RESET 0x1f /* Issue a read to reset, a write to clear. */
54 #define AXNET_MII_EEP 0x14 /* Offset of MII access port */
55 #define AXNET_TEST 0x15 /* Offset of TEST Register port */
56 #define AXNET_GPIO 0x17 /* Offset of General Purpose Register Port */
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Donnn,nb7vpq904m.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ON Semiconductor Type-C DisplayPort ALT Mode Linear Redriver
10 - Neil Armstrong <neil.armstrong@linaro.org>
15 - onnn,nb7vpq904m
20 vcc-supply:
23 enable-gpios: true
25 retimer-switch:
29 orientation-switch:
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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra210-admaif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^admaif@[0-9a-f]*$"
26 - enum:
27 - nvidia,tegra210-admaif
28 - nvidia,tegra186-admaif
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H A Dnvidia,tegra-audio-graph-card.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-graph-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Jon Hunter <jonathanh@nvidia.com>
16 - Sameer Pujar <spujar@nvidia.com>
19 - $ref: audio-graph.yaml#
24 - nvidia,tegra210-audio-graph-card
25 - nvidia,tegra186-audio-graph-card
30 clock-names:
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/openbmc/linux/include/sound/
H A Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define AK4114_REG_PWRDN 0x00 /* power down */
12 #define AK4114_REG_FORMAT 0x01 /* format control */
13 #define AK4114_REG_IO0 0x02 /* input/output control */
14 #define AK4114_REG_IO1 0x03 /* input/output control */
15 #define AK4114_REG_INT0_MASK 0x04 /* interrupt0 mask */
16 #define AK4114_REG_INT1_MASK 0x05 /* interrupt1 mask */
17 #define AK4114_REG_RCS0 0x06 /* receiver status 0 */
18 #define AK4114_REG_RCS1 0x07 /* receiver status 1 */
19 #define AK4114_REG_RXCSB0 0x08 /* RX channel status byte 0 */
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/openbmc/linux/sound/firewire/dice/
H A Ddice-alesis.c1 // SPDX-License-Identifier: GPL-2.0
3 * dice-alesis.c - a part of driver for DICE based devices
13 {8, 4, 0}, /* Tx1 = ADAT1. */
19 {16, 4, 0}, /* Tx1 = ADAT1 + ADAT2 (available at low rate). */
31 if (err < 0) in snd_dice_detect_alesis_formats()
36 memcpy(dice->tx_pcm_chs, alesis_io14_tx_pcm_chs, in snd_dice_detect_alesis_formats()
40 memcpy(dice->tx_pcm_chs, alesis_io26_tx_pcm_chs, in snd_dice_detect_alesis_formats()
45 for (i = 0; i < SND_DICE_RATE_MODE_COUNT; ++i) in snd_dice_detect_alesis_formats()
46 dice->rx_pcm_chs[0][i] = 8; in snd_dice_detect_alesis_formats()
48 dice->tx_midi_ports[0] = 1; in snd_dice_detect_alesis_formats()
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/openbmc/linux/sound/soc/codecs/
H A Drk817_codec.c1 // SPDX-License-Identifier: GPL-2.0
33 * I don't have another implementation to compare from the Rockchip sources. Hard-coding for now.
42 snd_soc_component_write(component, RK817_CODEC_DDAC_POPD_DACST, 0x02); in rk817_init()
43 snd_soc_component_write(component, RK817_CODEC_DDAC_SR_LMT0, 0x02); in rk817_init()
44 snd_soc_component_write(component, RK817_CODEC_DADC_SR_ACL0, 0x02); in rk817_init()
45 snd_soc_component_write(component, RK817_CODEC_DTOP_VUCTIME, 0xf4); in rk817_init()
46 if (rk817->mic_in_differential) { in rk817_init()
51 return 0; in rk817_init()
59 snd_soc_component_write(component, RK817_CODEC_APLL_CFG1, 0x58); in rk817_set_component_pll()
61 snd_soc_component_write(component, RK817_CODEC_APLL_CFG2, 0x2d); in rk817_set_component_pll()
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H A Dcs35l41.c1 // SPDX-License-Identifier: GPL-2.0
3 // cs35l41.c -- CS35l41 ALSA SoC audio driver
5 // Copyright 2017-2021 Cirrus Logic, Inc.
23 #include <sound/soc-dapm.h>
39 { 32768, 0x00 },
40 { 8000, 0x01 },
41 { 11025, 0x02 },
42 { 12000, 0x03 },
43 { 16000, 0x04 },
44 { 22050, 0x05 },
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H A Dtwl4030.c1 // SPDX-License-Identifier: GPL-2.0-only
28 #include <linux/mfd/twl4030-audio.h>
31 #define TWL4030_PMBR1_REG 0x0D
33 #define TWL4030_GPIO6_PWM0_MUTE(value) ((value & 0x03) << 2)
67 u8 ctl_cache[TWL4030_REG_PRECKR_CTL - TWL4030_REG_EAR_CTL + 1];
79 twl4030->ctl_cache[i - TWL4030_REG_EAR_CTL] = byte; in tw4030_init_ctl_cache()
86 u8 value = 0; in twl4030_read()
89 return -EIO; in twl4030_read()
98 value = twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL]; in twl4030_read()
116 if (twl4030->earpiece_enabled) in twl4030_can_write_to_chip()
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/openbmc/linux/arch/x86/crypto/
H A Dtwofish-x86_64-asm_64-3way.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Twofish Cipher 3-way parallel algorithm (x86_64)
10 .file "twofish-x86_64-asm-3way.S"
14 #define s0 0
22 3-way twofish
43 #define CD0 0x0(%rsp)
44 #define CD1 0x8(%rsp)
45 #define CD2 0x10(%rsp)
93 #define g1g2_3(ab, cd, Tx0, Tx1, Tx2, Tx3, Ty0, Ty1, Ty2, Ty3, x, y) \ argument
95 do16bit_ror(32, mov, xor, Tx0, Tx1, RT0, x ## 0, ab ## 0, x ## 0); \
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/openbmc/linux/arch/powerpc/boot/dts/
H A Dtqm8xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
28 PowerPC,860@0 {
30 reg = <0x0>;
31 d-cache-line-size = <16>; // 16 bytes
32 i-cache-line-size = <16>; // 16 bytes
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/openbmc/u-boot/drivers/net/
H A Dne2000_base.c2 Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
16 -------------------------------------------
31 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
44 at http://sources.redhat.com/ecos/ecos-license/
45 -------------------------------------------
49 -------------------------------------------
54 -------------------------------------------
62 Date: 2001-06-13
114 base = dp->base; in dp83902a_init()
125 for (i = 0; i < 6; i++) in dp83902a_init()
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/openbmc/linux/include/linux/can/platform/
H A Dsja1000.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #define CDR_CLKOUT_MASK 0x07
7 #define CDR_CLK_OFF 0x08 /* Clock off (CLKOUT pin) */
8 #define CDR_RXINPEN 0x20 /* TX1 output is RX irq output */
9 #define CDR_CBP 0x40 /* CAN input comparator bypass */
10 #define CDR_PELICAN 0x80 /* PeliCAN mode */
13 #define OCR_MODE_BIPHASE 0x00
14 #define OCR_MODE_TEST 0x01
15 #define OCR_MODE_NORMAL 0x02
16 #define OCR_MODE_CLOCK 0x03
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