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/openbmc/linux/include/linux/dma/
H A Dsprd-dma.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * The Spreadtrum DMA controller supports channel 2-stage tansfer, that means
19 * trigger the destination channel's transaction automatically by hardware
22 * To support 2-stage tansfer, we must configure the channel mode and trigger
27 * enum sprd_dma_chn_mode: define the DMA channel mode for 2-stage transfer
29 * support the 2-stage transfer.
35 * Now the DMA controller can supports 2 groups 2-stage transfer.
46 * enum sprd_dma_trg_mode: define the DMA channel trigger mode for 2-stage
48 * @SPRD_DMA_NO_TRG: No trigger setting.
49 * @SPRD_DMA_FRAG_DONE_TRG: Trigger the transaction of destination channel
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dstm32mp157c.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap5-uevm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
7 #include "omap5-board-common.dtsi"
11 compatible = "ti,omap5-uevm", "ti,omap5";
18 reserved-memory {
19 #address-cells = <2>;
20 #size-cells = <2>;
23 dsp_memory_region: dsp-memory@95000000 {
24 compatible = "shared-dma-pool";
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/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
13 a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
19 output hardware trigger signals. CTIs can have a maximum number of input and
20 output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The
30 In general the connections between CTI and components via the trigger signals
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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dst,stm32-lptimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-lptimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Low-Power Timers
10 The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
12 - PWM output (with programmable prescaler, configurable polarity)
13 - Trigger source for STM32 ADC/DAC (LPTIM_OUT)
14 - Several counter modes:
15 - quadrature encoder to detect angular position and direction of rotary
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/openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Ddbg-tlv.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2018-2022 Intel Corporation
34 * struct iwl_fw_ini_header - Common Header for all ini debug TLV's structures
46 * struct iwl_fw_ini_region_dev_addr - Configuration to read device addresses
49 * @offset: offset to add to the base address of each chunk
57 * struct iwl_fw_ini_region_fifos - Configuration to read Tx/Rx fifos
70 * struct iwl_fw_ini_region_err_table - error table region data
75 * @base_addr: base address of the error table
87 * struct iwl_fw_ini_region_special_device_memory - special device memory
93 * @base_addr: base address of the error table
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/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm47081-luxul-xwr-1200.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
9 #include "bcm5301x-nand-cs0-bch4.dtsi"
12 compatible = "luxul,xwr-1200-v1", "brcm,bcm47081", "brcm,bcm4708";
13 model = "Luxul XWR-1200 V1";
29 #nvmem-cell-cells = <1>;
34 compatible = "gpio-leds";
36 led-power {
39 linux,default-trigger = "default-on";
42 led-lan3 {
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H A Dbcm47094-luxul-xwr-3150-v1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
9 #include "bcm5301x-nand-cs0-bch8.dtsi"
12 compatible = "luxul,xwr-3150-v1", "brcm,bcm47094", "brcm,bcm4708";
13 model = "Luxul XWR-3150 V1";
30 #nvmem-cell-cells = <1>;
35 compatible = "gpio-leds";
37 led-power {
40 linux,default-trigger = "default-on";
43 led-usb3 {
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H A Dbcm47094-dlink-dir-890l.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Device tree for D-Link DIR-890L
4 * D-Link calls this board "WRGAC36"
5 * this router has the same looks and form factor as D-Link DIR-885L.
7 * Some differences from DIR-885L include a separate USB2 port, separate LEDs
13 * Based on the device tree for DIR-885L
18 /dts-v1/;
21 #include "bcm5301x-nand-cs0-bch1.dtsi"
24 compatible = "dlink,dir-890l", "brcm,bcm47094", "brcm,bcm4708";
25 model = "D-Link DIR-890L";
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H A Dbcm53573.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
21 stdout-path = "serial0:115200n8";
25 #address-cells = <1>;
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/openbmc/linux/drivers/net/phy/
H A Ddp83640_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define PTP_TSTS 0x0017 /* PTP Trigger Status Register */
20 #define PTP_TXTS 0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */
21 #define PTP_RXTS 0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */
26 #define PTP_TRIG 0x0014 /* PTP Trigger Configuration Register */
57 #define TRIG_SEL_SHIFT (10) /* PTP Trigger Select */
59 #define TRIG_DIS (1<<9) /* Disable PTP Trigger */
60 #define TRIG_EN (1<<8) /* Enable PTP Trigger */
61 #define TRIG_READ (1<<7) /* Read PTP Trigger */
62 #define TRIG_LOAD (1<<6) /* Load PTP Trigger */
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/openbmc/linux/Documentation/firmware-guide/acpi/apei/
H A Deinj.rst1 .. SPDX-License-Identifier: GPL-2.0
15 which shows that the BIOS is exposing an EINJ table - it is the
39 - available_error_type
47 0x00000002 Processor Uncorrectable non-fatal
50 0x00000010 Memory Uncorrectable non-fatal
53 0x00000080 PCI Express Uncorrectable non-fatal
56 0x00000400 Platform Uncorrectable non-fatal
63 - error_type
68 - error_inject
70 Write any integer to this file to trigger the error injection. Make
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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dcdns,qspi-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vaishnav Achath <vaishnav.a@ti.com>
13 - $ref: spi-controller.yaml#
14 - if:
18 const: xlnx,versal-ospi-1.0
21 - power-domains
22 - if:
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/openbmc/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_smi_events.h1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
3 * Copyright 2020-2022 Advanced Micro Devices, Inc.
33 unsigned long address, bool write_fault,
36 unsigned long address, bool migration);
41 uint32_t trigger);
44 uint32_t from, uint32_t to, uint32_t trigger);
46 uint32_t trigger);
50 unsigned long address, unsigned long last,
51 uint32_t trigger);
H A Dkfd_smi_events.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2020-2022 Advanced Micro Devices, Inc.
67 struct kfd_smi_client *client = filep->private_data; in kfd_smi_ev_poll()
70 poll_wait(filep, &client->wait_queue, wait); in kfd_smi_ev_poll()
72 spin_lock(&client->lock); in kfd_smi_ev_poll()
73 if (!kfifo_is_empty(&client->fifo)) in kfd_smi_ev_poll()
75 spin_unlock(&client->lock); in kfd_smi_ev_poll()
85 struct kfd_smi_client *client = filep->private_data; in kfd_smi_ev_read()
91 return -ENOMEM; in kfd_smi_ev_read()
96 spin_lock(&client->lock); in kfd_smi_ev_read()
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/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-l-50.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Check Point L-50 Board Description
7 /dts-v1/;
10 #include "kirkwood-6281.dtsi"
13 model = "Check Point L-50";
14 compatible = "checkpoint,l-50", "marvell,kirkwood-88f6281", "marvell,kirkwood";
23 stdout-path = &uart0;
27 pinctrl: pin-controller@10000 {
28 pinctrl-0 = <&pmx_led38 &pmx_sysrst &pmx_button29>;
29 pinctrl-names = "default";
[all …]
/openbmc/linux/arch/x86/kernel/acpi/
H A Dboot.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * boot.c - Architecture-Specific Low-Level ACPI Boot Support
22 #include <linux/efi-bgrt.h>
70 /* Physical address of the Multiprocessor Wakeup Structure mailbox */
72 /* Virtual address of the Multiprocessor Wakeup Structure mailbox */
80 * ->device_hotplug_lock
81 * ->acpi_ioapic_lock
82 * ->ioapic_lock
84 * ->acpi_ioapic_lock
85 * ->ioapic_mutex
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/openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/
H A Derror-dump.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2014, 2018-2022 Intel Corporation
4 * Copyright (C) 2014-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
17 * enum iwl_fw_error_dump_type - types of data in the dump file
18 * @IWL_FW_ERROR_DUMP_CSR: Control Status Registers - from offset 0
25 * @IWL_FW_ERROR_DUMP_PRPH: range of periphery registers - there can be several
37 * for that reason is not in use in any other place in the Linux Wi-Fi
67 * struct iwl_fw_error_dump_data - data for one type
79 * struct iwl_dump_file_name_info - data for dump file name addition
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/openbmc/linux/arch/arm64/boot/dts/broadcom/bcmbca/
H A Dbcm4906-netgear-r8000p.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
19 compatible = "gpio-leds";
21 led-power-white {
27 led-power-amber {
33 led-wps {
39 led-2ghz {
45 led-5ghz-1 {
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp131.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp13-clks.h>
8 #include <dt-bindings/reset/stm32mp13-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
[all …]
H A Dstm32f746.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "../armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
[all …]
H A Dstm32f429.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "../armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dmcfwdebug.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfdebug.h -- ColdFire Debug Module support.
17 #define MCFDEBUG_BAAR 0x5 /* BDM address attribute */
18 #define MCFDEBUG_AATR 0x6 /* Address attribute trigger */
19 #define MCFDEBUG_TDR 0x7 /* Trigger definition */
22 #define MCFDEBUG_ABHR 0xc /* High address breakpoint */
23 #define MCFDEBUG_ABLR 0xd /* Low address breakpoint */
27 /* Define some handy constants for the trigger definition register */
51 #define MCFDEBUG_TDR_EAI1 0x00000010 /* Enable address BP inverted */
53 #define MCFDEBUG_TDR_EAR1 0x00000008 /* Enable address BP range */
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/openbmc/qemu/target/riscv/
H A Ddebug.h2 * QEMU RISC-V Native Debug Support
38 TRIGGER_TYPE_NO_EXIST = 0, /* trigger does not exist */
39 TRIGGER_TYPE_AD_MATCH = 2, /* address/data match trigger */
40 TRIGGER_TYPE_INST_CNT = 3, /* instruction count trigger */
41 TRIGGER_TYPE_INT = 4, /* interrupt trigger */
42 TRIGGER_TYPE_EXCP = 5, /* exception trigger */
43 TRIGGER_TYPE_AD_MATCH6 = 6, /* new address/data match trigger */
44 TRIGGER_TYPE_EXT_SRC = 7, /* external source trigger */
45 TRIGGER_TYPE_UNAVAIL = 15, /* trigger exists, but unavailable */
51 DBG_ACTION_NONE = -1, /* sentinel value */
/openbmc/linux/drivers/acpi/apei/
H A Deinj.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * Copyright 2009-2010 Intel Corp.
26 #include "apei-internal.h"
81 * most will ignore the parameter and make their own choice of address
144 EINJ_TAB_ENTRY(einj_tab), einj_tab->entries); in einj_exec_ctx_init()
179 *t -= SLEEP_UNIT_MIN; in einj_timedout()
188 int offset = v5param->vendor_extension; in check_vendor_extension()
197 sbdf = v->pcie_sbdf; in check_vendor_extension()
201 v->vendor_id, v->device_id, v->rev_id); in check_vendor_extension()
212 for (i = 0; i < einj_tab->entries; i++) { in einj_get_parameter_address()
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