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/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dnonsec_virt.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * code for switching cores into non-secure state and into HYP mode
12 #include <asm/proc-armv/ptrace.h>
20 /* the vector table for secure state and HYP mode */
38 * secure monitor handler
39 * U-Boot calls this "software interrupt" in start.S
41 * to non-secure state.
51 @ Obtain a secure stack
77 @ FIQ preserved for secure mode
94 ands r4, r4, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits
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/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dsama5d2.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Chip-specific header file for the SAMA5D2 SoC
18 #define ATMEL_ID_PIT 3 /* Periodic Interval Timer Interrupt */
19 #define ATMEL_ID_WDT 4 /* Watchdog Timer Interrupt */
29 #define ATMEL_ID_MATRIX1 14 /* H32MX, 32-bit AHB Matrix */
30 #define ATMEL_ID_MATRIX0 15 /* H64MX, 64-bit AHB Matrix */
31 #define ATMEL_ID_SECUMOD 16 /* Secure Module */
32 #define ATMEL_ID_HSMC 17 /* Multi-bit ECC interrupt */
44 #define ATMEL_ID_TWIHS0 29 /* Two-wire Interface 0 */
45 #define ATMEL_ID_TWIHS1 30 /* Two-wire Interface 1 */
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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dti,timer-dm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI dual-mode timer
10 - Tony Lindgren <tony@atomide.com>
13 The TI dual-mode timer is a general purpose timer with PWM capabilities.
18 - items:
19 - enum:
20 - ti,am335x-timer
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H A Darm,arch_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM architected timer
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
14 or a memory mapped architected timer, which provides up to 8 frames with a
15 physical and optional virtual timer per frame.
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/openbmc/linux/arch/arm64/boot/dts/arm/
H A Dcorstone1000.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
21 stdout-path = "serial0:115200n8";
25 #address-cells = <1>;
26 #size-cells = <0>;
30 compatible = "arm,cortex-a35";
32 next-level-cache = <&L2_0>;
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/openbmc/u-boot/arch/arm/mach-uniphier/arm32/
H A Darm-mpcore.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2011-2014 Panasonic Corporation
21 /* SCU Invalidate All Registers in Secure State */
29 /* SCU Non-secure Access Control Register */
32 /* Global Timer */
35 /* Global Timer Counter Registers */
38 /* Global Timer Control Register */
40 /* Global Timer Interrupt Status Register */
45 /* Auto-increment Register */
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
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/openbmc/qemu/include/hw/watchdog/
H A Dcmsdk-apb-watchdog.h13 * This is a model of the "APB watchdog" which is part of the Cortex-M
14 * System Design Kit (CMSDK) and documented in the Cortex-M System
16 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
19 * + Clock input "WDOGCLK": clock for the watchdog's timer
25 * (For instance the IoTKit does this with the non-secure watchdog, so that
26 * secure code can control whether non-secure code can perform a system
39 #define TYPE_CMSDK_APB_WATCHDOG "cmsdk-apb-watchdog"
44 * cmsdk-apb-watchdog device.
46 #define TYPE_LUMINARY_WATCHDOG "luminary-watchdog"
56 struct ptimer_state *timer; member
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Datmel-sysregs.txt4 - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid"
5 - reg : Should contain registers location and length
7 PIT Timer required properties:
8 - compatible: Should be "atmel,at91sam9260-pit"
9 - reg: Should contain registers location and length
10 - interrupts: Should contain interrupt for the PIT which is the IRQ line
13 PIT64B Timer required properties:
14 - compatible: Should be "microchip,sam9x60-pit64b"
15 - reg: Should contain registers location and length
16 - interrupts: Should contain interrupt for PIT64B timer
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/openbmc/linux/arch/arm/mach-at91/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M
147 bool "Periodic Interval Timer (PIT) support"
153 Timer. It has a relatively low resolution and the TC Block clocksource
157 bool "Timer Counter Blocks (TCB) support"
163 On platforms with 16-bit counters, two timer channels are combined
164 to make a single 32-bit timer.
168 bool "64-bit Periodic Interval Timer (PIT64B) support"
173 clocksource and clockevent (SAMA7G5) based on Microchip 64-bit
174 Periodic Interval Timer.
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/openbmc/linux/arch/arm/mach-shmobile/
H A Dsetup-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Generation 2 support
12 #include <linux/dma-map-ops.h>
23 #include "rcar-gen2.h"
26 { .compatible = "renesas,r8a7742-cpg-mssr", .data = "extal" },
27 { .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
28 { .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" },
29 { .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
30 { .compatible = "renesas,r8a7791-cpg-mssr", .data = "extal" },
31 { .compatible = "renesas,r8a7793-cpg-mssr", .data = "extal" },
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/openbmc/u-boot/arch/arm/mach-rockchip/
H A Drk322x-board-spl.c1 // SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/timer.h>
52 rk_clrsetreg(&grf->gpio1b_iomux, in board_debug_uart_init()
57 rk_clrsetreg(&grf->con_iomux, in board_debug_uart_init()
86 printf("timer init done\n"); in board_init_f()
93 /* Disable the ddr secure region setting to make it non-secure */ in board_init_f()
H A Drk3368-board-tpl.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <asm/arch/timer.h>
21 * The SPL (and also the full U-Boot stage on the RK3368) will run in
22 * secure mode (i.e. EL3) and an ATF will eventually be booted before
24 * here and rely on the ATF installing the final (secure) policy
53 /* Set all configurable IP to 'non secure'-mode */ in sgrf_init()
59 * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c in sgrf_init()
60 * Original comment: "ddr space set no secure mode" in sgrf_init()
66 /* Set 'secure dma' to 'non secure'-mode */ in sgrf_init()
72 rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ); in sgrf_init()
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/openbmc/u-boot/arch/arm/dts/
H A Dk3-am654-r5-base-board.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
6 /dts-v1/;
8 #include "k3-am654.dtsi"
9 #include "k3-am654-base-board-u-boot.dtsi"
10 #include "k3-am654-base-board-ddr4-1600MHz.dtsi"
11 #include "k3-am654-ddr.dtsi"
14 compatible = "ti,am654-evm", "ti,am654";
23 stdout-path = "serial2:115200n8";
24 tick-timer = &timer1;
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/openbmc/qemu/include/hw/intc/
H A Darmv7m_nvic.h13 #include "target/arm/cpu-qom.h"
15 #include "hw/timer/armv7m_systick.h"
27 /* Exception priorities can range from -3 to 255; only the unmodifiable
47 * a Secure and a NonSecure version of the exception and its state):
50 * they may be configurable to target either Secure or NonSecure state.
51 * We store the secure exception state in sec_vectors[] for the banked
53 * like SecureFault that unconditionally target Secure state).
54 * Entries in sec_vectors[] for non-banked exception numbers are unused.
66 * - vectpending
67 * - vectpending_is_secure
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/openbmc/qemu/tests/qtest/
H A Dsse-timer-test.c2 * QTest testcase for the SSE timer device
18 #include "libqtest-single.h"
21 * SSE-123/SSE-300 timer in the mps3-an547 board, where it is driven
26 /* PERIPHNSPPC0 register in the SSE-300 Secure Access Configuration block */
39 /* SSE timer register offsets */
59 * need to move the timer forward the specified number of ticks. in clock_step_ticks()
69 * Reset the system counter and the timer between tests. This in reset_counter_and_timer()
104 /* Basic timer functionality test */ in test_timer()
108 * The timer is behind a Peripheral Protection Controller, and in test_timer()
109 * qtest accesses are always non-secure (no memory attributes), in test_timer()
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/openbmc/linux/arch/arm64/boot/dts/intel/
H A Dkeembay-soc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
23 enable-method = "psci";
27 compatible = "arm,cortex-a53";
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/openbmc/u-boot/arch/arm/include/asm/
H A Dglobal_data.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2002-2010
10 /* Architecture-specific global data */
32 /* "static data" needed by most of timer.c on ARM platforms */
51 * Secure memory addr
53 * or if RAM splits into non-consecutive banks. It also has a
54 * flag indicating the secure memory is marked as secure by MMU.
64 * driver which continues to run after U-Boot exits.
83 #include <asm-generic/global_data.h>
97 * time of writing, clang: error: unknown argument: '-ffixed-x18' in get_gd()
/openbmc/u-boot/include/configs/
H A Dti_omap5_common.h1 /* SPDX-License-Identifier: GPL-2.0+ */
19 /* Use General purpose timer 1 */
24 * the timings to use or use pre-determined timings (based on using the
46 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
79 * reserved for secure world use and the flash loader image is
80 * preceded by a secure certificate. The SPL will therefore run in internal
85 /* If no specific start address is specified then the secure EMIF
87 * the main u-boot relocation from clobbering that memory and causing a
88 * firewall violation, we tell u-boot that memory is protected RAM (PRAM)
/openbmc/u-boot/arch/arm/include/asm/arch-omap4/
H A Domap.h1 /* SPDX-License-Identifier: GPL-2.0+ */
10 * Richard Woodruff <r-woodruff2@ti.com>
24 * L4 Peripherals - L4 Wakeup and L4 Core now
57 /* Watchdog Timer2 - MPU watchdog */
64 /* Watchdog Timer */
68 /* GP Timer */
106 * Non-secure SRAM Addresses
107 * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
113 #define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K)
/openbmc/qemu/include/hw/arm/
H A Darmsse.h2 * ARM SSE (Subsystems for Embedded): IoTKit, SSE-200
14 * hardware, which include the IoT Kit and the SSE-050, SSE-100 and
15 * SSE-200. Currently we model:
16 * - the Arm IoT Kit which is documented in
18 * - the SSE-200 which is documented in
22 * a Cortex-M33
29 * space are secure and non-secure aliases of each other
30 * The SSE-200 additionally contains:
31 * a second Cortex-M33
37 * per-CPU identity and control register blocks
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/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Damlogic,meson-vrtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/amlogic,meson-vrtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
17 application processors (AP) and the secure co-processor (SCP.) When
19 program an always-on timer before going sleep. When the timer expires,
23 - $ref: rtc.yaml#
28 - amlogic,meson-vrtc
34 - compatible
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/openbmc/linux/arch/arm64/boot/dts/tesla/
H A Dfsd.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2022 Tesla, Inc.
11 #include <dt-bindings/clock/fsd-clk.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
38 #address-cells = <2>;
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/openbmc/linux/drivers/acpi/arm64/
H A Dgtdt.c1 // SPDX-License-Identifier: GPL-2.0-only
23 * struct acpi_gtdt_descriptor - Store the key info of GTDT for all functions
26 * @platform_timer: The pointer to the start of Platform Timer Structure
43 platform_timer += gh->length; in next_platform_timer()
58 return gh->type == ACPI_GTDT_TYPE_TIMER_BLOCK; in is_timer_block()
66 if (gh->type != ACPI_GTDT_TYPE_WATCHDOG) in is_non_secure_watchdog()
69 return !(wd->timer_flags & ACPI_GTDT_WATCHDOG_SECURE); in is_non_secure_watchdog()
86 * acpi_gtdt_map_ppi() - Map the PPIs of per-cpu arch_timer.
89 * Note: Secure state is not managed by the kernel on ARM64 systems.
90 * So we only handle the non-secure timer PPIs,
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/openbmc/linux/drivers/clocksource/
H A Dtimer-ti-dm-systimer.c1 // SPDX-License-Identifier: GPL-2.0+
15 #include <linux/clk/clk-conf.h>
17 #include <clocksource/timer-ti-dm.h>
18 #include <dt-bindings/bus/ti-sysc.h>
34 * Subset of the timer registers we use. Note that the register offsets
35 * depend on the timer revision detected.
68 u32 tidr = readl_relaxed(t->base); in dmtimer_systimer_revision1()
82 writel_relaxed(val, t->base + t->sysc); in dmtimer_systimer_enable()
90 writel_relaxed(DMTIMER_TYPE1_DISABLE, t->base + t->sysc); in dmtimer_systimer_disable()
95 void __iomem *syss = t->base + OMAP_TIMER_V1_SYS_STAT_OFFSET; in dmtimer_systimer_type1_reset()
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