| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | cirrus,lochnagar.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/cirrus,lochnagar.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
15 Logic devices on mini-cards, as well as allowing connection of various
17 Audio system topology, clocking and power can all be controlled through
21 This binding document describes the binding for the clock portion of the
25 [1] Clock : ../clock/clock-bindings.txt
28 [2] include/dt-bindings/clock/lochnagar.h
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| H A D | lpc1850-cgu.txt | 1 * NXP LPC1850 Clock Generation Unit (CGU)
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
15 - Above text taken from NXP LPC1850 User Manual.
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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| H A D | renesas,emev2-smu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas EMMA Mobile EV2 System Management Unit
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
14 The System Management Unit is described in user's manual R19UH0037EJ1000_SMU.
15 This is not a clock provider, but clocks under SMU depend on it.
19 const: renesas,emev2-smu
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| H A D | baikal,bt1-ccu-pll.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
16 connected with an external fixed rate oscillator, which signal is transformed
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
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| H A D | canaan,k210-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/canaan,k210-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Canaan Kendryte K210 Clock
10 - Damien Le Moal <dlemoal@kernel.org>
13 Canaan Kendryte K210 SoC clocks driver bindings. The clock
15 system controller node.
18 - dt-bindings/clock/k210-clk.h
22 const: canaan,k210-clk
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| /openbmc/linux/Documentation/devicetree/bindings/ptp/ |
| H A D | ptp-qoriq.txt | 1 * Freescale QorIQ 1588 timer based PTP clock
5 - compatible Should be "fsl,etsec-ptp" for eTSEC
6 Should be "fsl,fman-ptp-timer" for DPAA FMan
7 Should be "fsl,dpaa2-ptp" for DPAA2
8 Should be "fsl,enetc-ptp" for ENETC
9 - reg Offset and length of the register set for the device
10 - interrupts There should be at least two interrupts. Some devices
13 Clock Properties:
15 - fsl,cksel Timer reference clock source.
16 - fsl,tclk-period Timer reference clock period in nanoseconds.
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| /openbmc/linux/Documentation/devicetree/bindings/sound/ |
| H A D | audio-graph-port.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/audio-graph-port.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
15 port-base:
16 $ref: /schemas/graph.yaml#/$defs/port-base
18 convert-rate:
19 $ref: /schemas/sound/dai-params.yaml#/$defs/dai-sample-rate
20 convert-channels:
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| H A D | simple-card.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 frame-master:
15 description: Indicates dai-link frame master.
18 bitclock-master:
19 description: Indicates dai-link bit clock master
22 frame-inversion:
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| /openbmc/linux/drivers/clk/baikal-t1/ |
| H A D | ccu-div.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Baikal-T1 CCU Dividers interface driver
10 #include <linux/clk-provider.h>
17 * CCU Divider private clock IDs
18 * @CCU_SYS_SATA_CLK: CCU SATA internal clock
19 * @CCU_SYS_XGMAC_CLK: CCU XGMAC internal clock
21 #define CCU_SYS_SATA_CLK -1
22 #define CCU_SYS_XGMAC_CLK -2
26 * @CCU_DIV_BASIC: Basic divider clock required by the kernel as early as
32 * @CCU_DIV_LOCK_SHIFTED: Find lock-bit at non-standard position.
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "Baikal-T1 Clocks Control Unit interface"
7 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
9 consists of multiple global clock domains, which can be reset by
12 configurable and fixed clock dividers. Enable this option to be able
13 to select Baikal-T1 CCU PLLs and Dividers drivers.
18 bool "Baikal-T1 CCU PLLs support"
22 Enable this to support the PLLs embedded into the Baikal-T1 SoC
23 System Controller. These are five PLLs placed at the root of the
27 CPUs, DDR, etc.) or passed over the clock dividers to be only
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| /openbmc/linux/Documentation/devicetree/bindings/mfd/ |
| H A D | cirrus,lochnagar.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
15 Logic devices on mini-cards, as well as allowing connection of
17 platform. Audio system topology, clocking and power can all be
25 [2] include/dt-bindings/pinctrl/lochnagar.h
26 [3] include/dt-bindings/clock/lochnagar.h
28 And these documents for the required sub-node binding details:
29 [4] Clock: ../clock/cirrus,lochnagar.yaml
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| /openbmc/linux/drivers/clk/mvebu/ |
| H A D | ap806-system-controller.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell Armada AP806 System Controller
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #define pr_fmt(fmt) "ap806-system-controller: " fmt
14 #include <linux/clk-provider.h>
99 return -EINVAL; in ap806_get_sar_clocks()
123 return -EINVAL; in ap807_get_sar_clocks()
134 struct device *dev = &pdev->dev; in ap806_syscon_common_probe()
135 struct device_node *np = dev->of_node; in ap806_syscon_common_probe()
154 if (of_device_is_compatible(pdev->dev.of_node, in ap806_syscon_common_probe()
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| /openbmc/linux/Documentation/devicetree/bindings/arm/marvell/ |
| H A D | ap80x-system-controller.txt | 1 Marvell Armada AP80x System Controller
5 7K/8K/931x SoCs. It contains system controllers, which provide several
6 registers giving access to numerous features: clocks, pin-muxing and
8 these system controllers.
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
14 SYSTEM CONTROLLER 0
18 -------
21 The Device Tree node representing the AP806/AP807 system controller
24 - 0: reference clock of CPU cluster 0
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| /openbmc/linux/arch/arm/boot/dts/broadcom/ |
| H A D | bcm-cygnus-clock.dtsi | 34 #address-cells = <1>;
35 #size-cells = <1>;
39 #clock-cells = <0>;
40 compatible = "fixed-clock";
41 clock-frequency = <25000000>;
46 #clock-cells = <0>;
47 compatible = "brcm,cygnus-armpll";
52 /* peripheral clock for system timer */
54 #clock-cells = <0>;
55 compatible = "fixed-factor-clock";
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| /openbmc/u-boot/doc/device-tree-bindings/clock/ |
| H A D | st,stm32mp1.txt | 1 STMicroelectronics STM32MP1 clock tree initialization
4 The STM32MP clock tree initialization is based on device tree information
5 for RCC IP and on fixed clocks.
7 -------------------------------
8 RCC CLOCK = st,stm32mp1-rcc-clk
9 -------------------------------
11 The RCC IP is both a reset and a clock controller but this documentation only
12 describes the fields added for clock tree initialization which are not present
15 Please refer to ../mfd/st,stm32-rcc.txt for all the other properties common
20 - compatible: Should be "st,stm32mp1-rcc-clk"
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| /openbmc/linux/drivers/clk/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
16 Select this option when the clock API in <linux/clk.h> is implemented
22 bool "Common Clock Framework"
28 The common clock framework is a single definition of struct
30 implementation of the clock API in include/linux/clk.h.
37 tristate "Clock driver for WM831x/2x PMICs"
50 This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
54 tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner"
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
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| /openbmc/linux/Documentation/arch/arm64/ |
| H A D | amu.rst | 9 Date: 2019-09-10
16 ---------------------
22 counters intended for system management use. The AMU extension provides a
23 system register interface to the counter registers and also supports an
24 optional external memory-mapped interface.
27 of four fixed and architecturally defined 64-bit event counters.
29 - CPU cycle counter: increments at the frequency of the CPU.
30 - Constant counter: increments at the fixed frequency of the system
31 clock.
32 - Instructions retired: increments with every architecturally executed
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| /openbmc/linux/arch/arm/boot/dts/mediatek/ |
| H A D | mt6580.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
15 interrupt-parent = <&sysirq>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
28 compatible = "arm,cortex-a7";
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| H A D | mt6582.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
13 interrupt-parent = <&sysirq>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a7";
26 compatible = "arm,cortex-a7";
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| H A D | mt6589.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&sysirq>;
18 #address-cells = <1>;
19 #size-cells = <0>;
20 enable-method = "mediatek,mt6589-smp";
24 compatible = "arm,cortex-a7";
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| H A D | mt6592.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&sysirq>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
28 compatible = "arm,cortex-a7";
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| /openbmc/linux/arch/arm64/boot/dts/freescale/ |
| H A D | fsl-ls1012a-frdm.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include "fsl-ls1012a.dtsi"
15 compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
17 sys_mclk: clock-mclk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <25000000>;
23 reg_1p8v: regulator-1p8v {
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| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | dra72-evm-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "dra7-ipu-dsp-common.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/clock/ti-dra7-atl.h>
13 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
20 stdout-path = &uart1;
23 evm_12v0: fixedregulator-evm12v0 {
25 compatible = "regulator-fixed";
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| /openbmc/linux/Documentation/devicetree/bindings/pwm/ |
| H A D | pwm-fsl-ftm.txt | 4 device tree provides a property to describing this so that an operating system
8 SoC | FTM-PWM endianness
9 --------+-------------------
19 - compatible : should be "fsl,<soc>-ftm-pwm" and one of the following
21 - "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610
22 - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM
23 - reg: Physical base address and length of the controller's registers
24 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
26 - clock-names: Should include the following module clock source entries:
27 "ftm_sys" (module clock, also can be used as counter clock),
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| /openbmc/linux/Documentation/devicetree/bindings/arm/calxeda/ |
| H A D | hb-sregs.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/calxeda/hb-sregs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda Highbank system registers
10 The Calxeda Highbank system has a block of MMIO registers controlling
11 several generic system aspects. Those can be used to control some power
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-sregs
28 - compatible
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