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/openbmc/linux/Documentation/devicetree/bindings/mailbox/
H A Dti,omap-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI OMAP2+ and K3 Mailbox devices
10 - Suman Anna <s-anna@ti.com>
13 The OMAP Mailbox hardware facilitates communication between different
14 processors using a queued mailbox interrupt mechanism. The IP block is
19 Each mailbox IP block/cluster has a certain number of h/w fifo queues and
35 lines can also be routed to different processor sub-systems on DRA7xx as they
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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
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H A Dti,k3-dsp-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
23 Each DSP Core sub-system is represented as a single DT node. Each node has a
29 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
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H A Dti,k3-r5f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
27 Each Dual-Core R5F sub-system is represented as a single DTS node
40 - ti,am62-r5fss
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H A Dqcom,sc7280-mss-pil.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sibi Sankar <quic_sibis@quicinc.com>
19 - qcom,sc7280-mss-pil
23 - description: MSS QDSP6 registers
24 - description: RMB registers
26 reg-names:
28 - const: qdsp6
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/openbmc/linux/include/linux/soc/mediatek/
H A Dmtk-cmdq.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/mailbox/mtk-cmdq-mailbox.h>
33 * cmdq_dev_get_client_reg() - parse cmdq client reg from the device
35 * @dev: device of CMDQ mailbox client
48 * cmdq_mbox_create() - create CMDQ mailbox client and channel
49 * @dev: device of CMDQ mailbox client
50 * @index: index of CMDQ mailbox channel
52 * Return: CMDQ mailbox client pointer
57 * cmdq_mbox_destroy() - destroy CMDQ mailbox client and channel
58 * @client: the CMDQ mailbox client
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/openbmc/linux/include/linux/platform_data/
H A Dwilco-ec.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 /* Message flags for using the mailbox() interface */
25 * struct wilco_ec_device - Wilco Embedded Controller handle.
27 * @mailbox_lock: Mutex to ensure one mailbox command at a time.
28 * @io_command: I/O port for mailbox command. Provided by ACPI.
29 * @io_data: I/O port for mailbox data. Provided by ACPI.
30 * @io_packet: I/O port for mailbox packet data. Provided by ACPI.
34 * @debugfs_pdev: The child platform_device used by the debugfs sub-driver.
35 * @rtc_pdev: The child platform_device used by the RTC sub-driver.
36 * @charger_pdev: Child platform_device used by the charger config sub-driver.
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/openbmc/linux/Documentation/devicetree/bindings/power/reset/
H A Dxlnx,zynqmp-power.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/xlnx,zynqmp-power.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 The zynqmp-power node describes the power management configurations.
18 const: xlnx,zynqmp-power
25 Standard property to specify a Mailbox. Each value of
27 mailbox controller device node and an args specifier
28 that will be the phandle to the intended sub-mailbox
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/openbmc/linux/Documentation/devicetree/bindings/firmware/
H A Darm,scpi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sudeep Holla <sudeep.holla@arm.com>
33 - const: arm,scpi # SCPI v1.0 and above
34 - const: arm,scpi-pre-1.0 # Unversioned SCPI before v1.0
35 - items:
36 - enum:
37 - amlogic,meson-gxbb-scpi
38 - const: arm,scpi-pre-1.0
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H A Darm,scmi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sudeep Holla <sudeep.holla@arm.com>
31 - description: SCMI compliant firmware with mailbox transport
33 - const: arm,scmi
34 - description: SCMI compliant firmware with ARM SMC/HVC transport
36 - const: arm,scmi-smc
37 - description: SCMI compliant firmware with ARM SMC/HVC transport
38 with shmem address(4KB-page, offset) as parameters
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/openbmc/linux/drivers/scsi/lpfc/
H A Dlpfc_mbox.c4 * Copyright (C) 2017-2022 Broadcom. All Rights Reserved. The term *
6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
9 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
17 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
47 * lpfc_mbox_rsrc_prep - Prepare a mailbox with DMA buffer memory.
49 * @mbox: pointer to the driver internal queue element for mailbox command.
51 * A mailbox command consists of the pool memory for the command, @mbox, and
69 return -ENOMEM; in lpfc_mbox_rsrc_prep()
71 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys); in lpfc_mbox_rsrc_prep()
72 if (!mp->virt) { in lpfc_mbox_rsrc_prep()
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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_opregion.c9 * distribute, sub license, and/or sell copies of the Software, and to
20 * NON-INFRINGEMENT. IN NO EVENT SHALL INTEL AND/OR ITS SUPPLIERS BE
52 #define MBOX_ACPI BIT(0) /* Mailbox #1 */
53 #define MBOX_SWSCI BIT(1) /* Mailbox #2 (obsolete from v2.x) */
54 #define MBOX_ASLE BIT(2) /* Mailbox #3 */
55 #define MBOX_ASLE_EXT BIT(4) /* Mailbox #5 */
56 #define MBOX_BACKLIGHT BIT(5) /* Mailbox #2 (valid from v3.x) */
79 /* OpRegion mailbox #1: public ACPI methods */
89 u32 aslp; /* ASL sleep time-out */
103 /* OpRegion mailbox #2: SWSCI */
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/openbmc/u-boot/doc/device-tree-bindings/firmware/
H A Dti,sci.txt1 Texas Instruments System Control Interface (TI-SCI) Message Protocol
2 --------------------------------------------------------------------
16 TI-SCI controller Device Node:
19 The TI-SCI node describes the Texas Instrument's System Controller entity node.
23 relationship between the TI-SCI parent node to the child node.
26 -------------------
27 - compatible: should be "ti,k2g-sci"
28 - mbox-names:
29 "rx" - Mailbox corresponding to receive path
30 "tx" - Mailbox corresponding to transmit path
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/openbmc/linux/drivers/net/ethernet/mellanox/mlxsw/
H A Dcmd.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
190 /* QUERY_FW - Query Firmware
191 * -------------------------
193 * -----------------------
212 * Firmware Revision - Major
217 * Firmware Sub-minor version (Patch level)
222 * Firmware Revision - Minor
233 * every time a non-backward-compatible change is done for the command
250 * Firmware timestamp - hour
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/openbmc/smbios-mdr/src/
H A Dsst_mailbox.cpp7 // http://www.apache.org/licenses/LICENSE-2.0
26 * Convenience RAII object for Wake-On-PECI (WOP) management, since PECI Config
27 * Local accesses to the OS Mailbox require the package to pop up to PC2. Also
28 * provides PCode OS Mailbox routine.
68 // PECI completion code defined in peci-ioctl.h which is not available in isSleeping()
79 * Send a single PECI PCS write to modify the Wake-On-PECI mode bit
89 throw PECIError("Failed to set Wake-On-PECI mode bit"); in setWakeOnPECI()
98 // PCode OS Mailbox interface register locations
139 throw PECIError("Failed to write mailbox reg"); in wrMailboxReg()
172 throw PECIError("Failed to read mailbox reg"); in rdMailboxReg()
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/openbmc/qemu/hw/misc/
H A Dmchp_pfsoc_ioscb.c33 * named as "System Port 0 (AXI-D0)".
43 * There are many sub-modules in the IOSCB module.
47 * The following are sub-modules offsets that are of concern.
188 qemu_irq_raise(s->irq); in mchp_pfsoc_ctrl_write()
209 memory_region_init(&s->container, OBJECT(s), in mchp_pfsoc_ioscb_realize()
211 sysbus_init_mmio(sbd, &s->container); in mchp_pfsoc_ioscb_realize()
213 /* add subregions for all sub-modules in IOSCB */ in mchp_pfsoc_ioscb_realize()
215 memory_region_init_io(&s->lane01, OBJECT(s), &mchp_pfsoc_dummy_ops, s, in mchp_pfsoc_ioscb_realize()
217 memory_region_add_subregion(&s->container, IOSCB_LANE01_BASE, &s->lane01); in mchp_pfsoc_ioscb_realize()
219 memory_region_init_io(&s->lane23, OBJECT(s), &mchp_pfsoc_dummy_ops, s, in mchp_pfsoc_ioscb_realize()
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/openbmc/linux/drivers/net/ethernet/intel/fm10k/
H A Dfm10k_mbx.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2019 Intel Corporation. */
7 * fm10k_fifo_init - Initialize a message FIFO
10 * @size: maximum message size to store in FIFO, must be 2^n - 1
14 fifo->buffer = buffer; in fm10k_fifo_init()
15 fifo->size = size; in fm10k_fifo_init()
16 fifo->head = 0; in fm10k_fifo_init()
17 fifo->tail = 0; in fm10k_fifo_init()
21 * fm10k_fifo_used - Retrieve used space in FIFO
28 return fifo->tail - fifo->head; in fm10k_fifo_used()
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Domap-usb.txt4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
5 - ti,hwmods : must be "usb_otg_hs"
6 - multipoint : Should be "1" indicating the musb controller supports
7 multipoint. This is a MUSB configuration-specific setting.
8 - num-eps : Specifies the number of endpoints. This is also a
9 MUSB configuration-specific setting. Should be set to "16"
10 - ram-bits : Specifies the ram address size. Should be set to "12"
11 - interface-type : This is a board specific setting to describe the type of
14 - mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
16 - power : Should be "50". This signifies the controller can supply up to
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/openbmc/linux/include/uapi/linux/
H A Disst_if.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
16 * struct isst_if_platform_info - Define platform information
25 * @mmio_supported: Support of mmio interface for core-power feature
40 * struct isst_if_cpu_map - CPU mapping between logical and physical CPU
53 * struct isst_if_cpu_maps - structure for CPU map IOCTL
67 * struct isst_if_io_reg - Read write PUNIT IO register
84 * struct isst_if_io_regs - structure for IO register commands
99 * struct isst_if_mbox_cmd - Structure to define mail box command
101 * @parameter: Mailbox parameter value
102 * @req_data: Request data for the mailbox
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/openbmc/linux/drivers/crypto/bcm/
H A Dcipher.h2 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <linux/mailbox/brcm-message.h>
41 /* size of salt value for AES-GCM-ESP and AES-CCM-ESP */
53 * Maximum number of bytes from a non-final hash request that can be deferred
59 /* Force at least 4-byte alignment of all SPU message fields */
62 /* Number of times to resend mailbox message if mb queue is full */
80 * SPUM_NS2 and SPUM_NSP are the SPU-M block on Northstar 2 and Northstar Plus,
126 * SPU request message header. For SPU-M, holds MH, EMH, SCTX, BDESC,
140 /* SPU-M request message STATUS field */
159 * -OR- tweak value when XTS/AES is used
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/openbmc/linux/drivers/platform/x86/intel/speed_select_if/
H A Disst_if_common.c1 // SPDX-License-Identifier: GPL-2.0
23 #include <asm/intel-family.h>
93 return -ENOMEM; in isst_store_new_cmd()
95 sst_cmd->cpu = cpu; in isst_store_new_cmd()
96 sst_cmd->cmd = cmd; in isst_store_new_cmd()
97 sst_cmd->mbox_cmd_type = mbox_cmd_type; in isst_store_new_cmd()
98 sst_cmd->param = param; in isst_store_new_cmd()
99 sst_cmd->data = data; in isst_store_new_cmd()
101 hash_add(isst_hash, &sst_cmd->hnode, sst_cmd->cmd); in isst_store_new_cmd()
113 hash_del(&sst_cmd->hnode); in isst_delete_hash()
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/openbmc/linux/drivers/staging/qlge/
H A Dqlge_mpi.c1 // SPDX-License-Identifier: GPL-2.0
8 /* Un-pause the RISC */ in qlge_unpause_mpi_risc()
11 return -EIO; in qlge_unpause_mpi_risc()
24 for (count = UDELAY_COUNT; count; count--) { in qlge_pause_mpi_risc()
30 return (count == 0) ? -ETIMEDOUT : 0; in qlge_pause_mpi_risc()
40 for (count = UDELAY_COUNT; count; count--) { in qlge_hard_reset_mpi_risc()
48 return (count == 0) ? -ETIMEDOUT : 0; in qlge_hard_reset_mpi_risc()
107 if (qdev->func < qdev->alt_func) in qlge_own_firmware()
116 if (!(temp & (1 << (8 + qdev->alt_func)))) in qlge_own_firmware()
128 return -EBUSY; in qlge_get_mb_sts()
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/openbmc/linux/drivers/net/ethernet/hisilicon/hns3/hns3vf/
H A Dhclgevf_mbx.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
13 return resp_code ? -resp_code : 0; in hclgevf_resp_to_errno()
22 hdev->mbx_resp.received_resp = false; in hclgevf_reset_mbx_resp_status()
23 hdev->mbx_resp.origin_mbx_msg = 0; in hclgevf_reset_mbx_resp_status()
24 hdev->mbx_resp.resp_status = 0; in hclgevf_reset_mbx_resp_status()
25 hdev->mbx_resp.match_id++; in hclgevf_reset_mbx_resp_status()
27 if (hdev->mbx_resp.match_id == 0) in hclgevf_reset_mbx_resp_status()
28 hdev->mbx_resp.match_id = HCLGEVF_MBX_MATCH_ID_START; in hclgevf_reset_mbx_resp_status()
29 memset(hdev->mbx_resp.additional_info, 0, HCLGE_MBX_MAX_RESP_DATA_SIZE); in hclgevf_reset_mbx_resp_status()
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/openbmc/qemu/scripts/
H A Dget_maintainer.pl9 # perl scripts/get_maintainer.pl [OPTIONS] -f <file>
36 my $email_git_since = "1-year-ago";
37 my $email_hg_since = "-365";
68 push(@signature_tags, "Signed-off-by:");
69 push(@signature_tags, "Reviewed-by:");
70 push(@signature_tags, "Acked-by:");
74 # rfc822 email address - preloaded methods go here.
76 my $rfc822_char = '[\\000-\\377]';
78 # VCS command support: class-like functions and strings
84 "available" => '(which("git") ne "") && (-e ".git")',
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/openbmc/linux/drivers/cxl/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
23 The CXL specification defines a "CXL memory device" sub-class in the
26 memory to be mapped into the system address map (Host-managed Device
31 and management primarily via the mailbox interface. See Chapter 2.3
64 (https://www.computeexpresslink.org/spec-landing). The CXL core
92 known as HDM "Host-managed Device Memory".
118 system-physical address range. For CXL regions established by
119 platform-firmware this option enables memory error handling to
121 range. Otherwise, platform-firmware managed CXL is enabled by being

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