| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | spi-fsl-dspi.txt | 4 - compatible : must be one of:
5 "fsl,vf610-dspi",
6 "fsl,ls1021a-v1.0-dspi",
7 "fsl,ls1012a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
8 "fsl,ls1028a-dspi",
9 "fsl,ls1043a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
10 "fsl,ls1046a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
11 "fsl,ls1088a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
12 "fsl,ls2080a-dspi" (optionally followed by "fsl,ls2085a-dspi"),
13 "fsl,ls2085a-dspi",
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| H A D | spi-lantiq-ssc.txt | 1 Lantiq Synchronous Serial Controller (SSC) SPI master driver
4 - compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
5 "intel,lgm-spi"
6 - #address-cells: see spi-bus.txt
7 - #size-cells: see spi-bus.txt
8 - reg: address and length of the spi master registers
9 - interrupts:
10 For compatible "intel,lgm-ssc" - the common interrupt number for
18 - clocks: spi clock phandle
19 - num-cs: see spi-bus.txt, set to 8 if unset
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| H A D | spi-cadence.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-cadence.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence SPI controller
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - cdns,spi-r1p6
19 - xlnx,zynq-spi-r1p6
27 clock-names:
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| H A D | spi-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-GPIO
10 - Rob Herring <robh@kernel.org>
13 This represents a group of 3-n GPIO lines used for bit-banged SPI on
17 - $ref: /schemas/spi/spi-controller.yaml#
21 const: spi-gpio
23 sck-gpios:
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| H A D | spi-davinci.txt | 1 Davinci SPI controller device bindings
4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
10 address on the SPI bus. Should be set to 1.
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
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| H A D | spi-fsl-lpspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Low Power SPI (LPSPI) for i.MX
10 - Anson Huang <Anson.Huang@nxp.com>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - enum:
19 - fsl,imx7ulp-spi
20 - fsl,imx8qxp-spi
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| H A D | samsung,spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/samsung,spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC SPI controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 All the SPI controller nodes should be represented in the aliases node using
14 the following format 'spi{n}' where n is a unique number for the alias.
19 - enum:
20 - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450
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| H A D | spi-armada-3700.txt | 1 * Marvell Armada 3700 SPI Controller
5 - compatible: should be "marvell,armada-3700-spi"
6 - reg: physical base address of the controller and length of memory mapped
8 - interrupts: The interrupt number. The interrupt specifier format depends on
10 - clocks: Must contain the clock source, usually from the North Bridge clocks.
11 - num-cs: The number of chip selects that is supported by this SPI Controller
12 - #address-cells: should be 1.
13 - #size-cells: should be 0.
17 spi0: spi@10600 {
18 compatible = "marvell,armada-3700-spi";
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| H A D | fsl-spi.txt | 1 * SPI (Serial Peripheral Interface)
4 - cell-index : QE SPI subblock index.
7 - compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl".
8 - mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
9 - reg : Offset and length of the register set for the device
10 - interrupts : <a b> where a is the interrupt number and b is a
15 - clock-frequency : input clock frequency to non FSL_SOC cores
18 - cs-gpios : specifies the gpio pins to be used for chipselects.
19 The gpios will be referred to as reg = <index> in the SPI child nodes.
20 If unspecified, a single SPI device without a chip select can be used.
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| H A D | socionext,f-ospi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/socionext,f-ospi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 memories using the SPI communication interface.
14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
17 - $ref: spi-controller.yaml#
21 const: socionext,f-ospi
29 num-cs:
34 - compatible
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| H A D | snps,dw-apb-ssi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
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| H A D | spi-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Controller Common Properties
10 - Mark Brown <broonie@kernel.org>
13 SPI busses can be described with a node for the SPI controller device
14 and a set of child nodes for each SPI slave on the bus. The system SPI
15 controller may be described for use in SPI master mode or in SPI slave mode,
20 pattern: "^spi(@.*|-([0-9]|[1-9][0-9]+))?$"
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| /openbmc/u-boot/doc/device-tree-bindings/spi/ |
| H A D | spi-zynq.txt | 1 Cadence SPI controller Device Tree Bindings
2 -------------------------------------------
5 - compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
6 - reg : Physical base address and size of SPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - interrupt-parent : Must be core interrupt controller
10 - clock-names : List of input clock names - "ref_clk", "pclk"
12 - clocks : Clock phandles (see clock bindings for details).
13 - spi-max-frequency : Maximum SPI clocking speed of device in Hz
16 - num-cs : Number of chip selects used.
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| H A D | spi-atcspi200.txt | 1 Andestech ATCSPI200 SPI controller Device Tree Bindings
2 -------------------------------------------------------
3 ATCSPI200 is a Serial Peripheral Interface (SPI) controller
4 which serves as a SPI master or a SPI slave.
9 - compatible: has to be "andestech,atcspi200".
10 - reg: Base address and size of the controllers memory area.
11 - #address-cells: <1>, as required by generic SPI binding.
12 - #size-cells: <0>, also as required by generic SPI binding.
13 - interrupts: Property with a value describing the interrupt number.
14 - clocks: Clock phandles (see clock bindings for details).
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| H A D | spi-bus.txt | 1 SPI (Serial Peripheral Interface) busses
3 SPI busses can be described with a node for the SPI master device
4 and a set of child nodes for each SPI slave on the bus. For this
5 discussion, it is assumed that the system's SPI controller is in
6 SPI master mode. This binding does not describe SPI controllers
9 The SPI master node requires the following properties:
10 - #address-cells - number of cells required to define a chip select
11 address on the SPI bus.
12 - #size-cells - should be zero.
13 - compatible - name of SPI bus controller following generic names
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | keystone-k2g.dtsi | 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&gic>;
34 #address-cells = <1>;
35 #size-cells = <0>;
37 interrupt-parent = <&gic>;
40 compatible = "arm,cortex-a15";
46 gic: interrupt-controller {
47 compatible = "arm,cortex-a15-gic";
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| H A D | keystone-k2l.dtsi | 13 #address-cells = <1>;
14 #size-cells = <0>;
16 interrupt-parent = <&gic>;
19 compatible = "arm,cortex-a15";
25 compatible = "arm,cortex-a15";
32 /include/ "keystone-k2l-clocks.dtsi"
36 current-speed = <115200>;
37 reg-shift = <2>;
38 reg-io-width = <4>;
46 current-speed = <115200>;
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| H A D | bk4r1.dts | 1 // SPDX-License-Identifier: GPL-2.0+ OR X11
6 /dts-v1/;
10 model = "Phytec phyCORE-Vybrid";
14 stdout-path = &uart1;
28 bus-num = <0>;
29 num-cs = <2>;
33 #address-cells = <1>;
34 #size-cells = <1>;
35 compatible = "spi-flash";
36 spi-max-frequency = <108000000>;
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| /openbmc/linux/arch/riscv/boot/dts/canaan/ |
| H A D | sipeed_maix_bit.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
17 compatible = "sipeed,maix-bit", "sipeed,maix-bitm",
18 "canaan,kendryte-k210";
22 stdout-path = "serial0:115200n8";
25 gpio-leds {
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| H A D | sipeed_maix_dock.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
17 compatible = "sipeed,maix-dock-m1", "sipeed,maix-dock-m1w",
18 "canaan,kendryte-k210";
22 stdout-path = "serial0:115200n8";
25 gpio-leds {
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| H A D | sipeed_maix_go.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
17 compatible = "sipeed,maix-go", "canaan,kendryte-k210";
21 stdout-path = "serial0:115200n8";
24 gpio-leds {
25 compatible = "gpio-leds";
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| H A D | sipeed_maixduino.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
16 compatible = "sipeed,maixduino", "canaan,kendryte-k210";
20 stdout-path = "serial0:115200n8";
23 gpio-keys {
24 compatible = "gpio-keys";
26 key-boot {
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| H A D | canaan_kd233.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
16 compatible = "canaan,kendryte-kd233", "canaan,kendryte-k210";
20 stdout-path = "serial0:115200n8";
23 gpio-leds {
24 compatible = "gpio-leds";
35 gpio-keys {
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| /openbmc/linux/Documentation/devicetree/bindings/gpio/ |
| H A D | spear_spics.txt | 1 === ST Microelectronics SPEAr SPI CS Driver ===
4 Cell spi controller through its system registers, which otherwise remains under
7 desired by some of the device protocols above spi which expect (multiple)
17 * compatible: should be defined as "st,spear-spics-gpio"
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
24 * gpio-controller: Marks the device node as gpio controller
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| /openbmc/linux/arch/arm64/boot/dts/toshiba/ |
| H A D | tmpv7708.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
10 #include <dt-bindings/clock/toshiba,tmpv770x.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
23 #size-cells = <0>;
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