1*b53bc281SShiraz Hashim=== ST Microelectronics SPEAr SPI CS Driver === 2*b53bc281SShiraz Hashim 3*b53bc281SShiraz HashimSPEAr platform provides a provision to control chipselects of ARM PL022 Prime 4*b53bc281SShiraz HashimCell spi controller through its system registers, which otherwise remains under 5*b53bc281SShiraz HashimPL022 control. If chipselect remain under PL022 control then they would be 6*b53bc281SShiraz Hashimreleased as soon as transfer is over and TxFIFO becomes empty. This is not 7*b53bc281SShiraz Hashimdesired by some of the device protocols above spi which expect (multiple) 8*b53bc281SShiraz Hashimtransfers without releasing their chipselects. 9*b53bc281SShiraz Hashim 10*b53bc281SShiraz HashimChipselects can be controlled by software by turning them as GPIOs. SPEAr 11*b53bc281SShiraz Hashimprovides another interface through system registers through which software can 12*b53bc281SShiraz Hashimdirectly control each PL022 chipselect. Hence, it is natural for SPEAr to export 13*b53bc281SShiraz Hashimthe control of this interface as gpio. 14*b53bc281SShiraz Hashim 15*b53bc281SShiraz HashimRequired properties: 16*b53bc281SShiraz Hashim 17*b53bc281SShiraz Hashim * compatible: should be defined as "st,spear-spics-gpio" 18*b53bc281SShiraz Hashim * reg: mentioning address range of spics controller 19*b53bc281SShiraz Hashim * st-spics,peripcfg-reg: peripheral configuration register offset 20*b53bc281SShiraz Hashim * st-spics,sw-enable-bit: bit offset to enable sw control 21*b53bc281SShiraz Hashim * st-spics,cs-value-bit: bit offset to drive chipselect low or high 22*b53bc281SShiraz Hashim * st-spics,cs-enable-mask: chip select number bit mask 23*b53bc281SShiraz Hashim * st-spics,cs-enable-shift: chip select number program offset 24*b53bc281SShiraz Hashim * gpio-controller: Marks the device node as gpio controller 25*b53bc281SShiraz Hashim * #gpio-cells: should be 1 and will mention chip select number 26*b53bc281SShiraz Hashim 27*b53bc281SShiraz HashimAll the above bit offsets are within peripcfg register. 28*b53bc281SShiraz Hashim 29*b53bc281SShiraz HashimExample: 30*b53bc281SShiraz Hashim------- 31*b53bc281SShiraz Hashimspics: spics@e0700000{ 32*b53bc281SShiraz Hashim compatible = "st,spear-spics-gpio"; 33*b53bc281SShiraz Hashim reg = <0xe0700000 0x1000>; 34*b53bc281SShiraz Hashim st-spics,peripcfg-reg = <0x3b0>; 35*b53bc281SShiraz Hashim st-spics,sw-enable-bit = <12>; 36*b53bc281SShiraz Hashim st-spics,cs-value-bit = <11>; 37*b53bc281SShiraz Hashim st-spics,cs-enable-mask = <3>; 38*b53bc281SShiraz Hashim st-spics,cs-enable-shift = <8>; 39*b53bc281SShiraz Hashim gpio-controller; 40*b53bc281SShiraz Hashim #gpio-cells = <2>; 41*b53bc281SShiraz Hashim}; 42*b53bc281SShiraz Hashim 43*b53bc281SShiraz Hashim 44*b53bc281SShiraz Hashimspi0: spi@e0100000 { 45*b53bc281SShiraz Hashim num-cs = <3>; 46*b53bc281SShiraz Hashim cs-gpios = <&gpio1 7 0>, <&spics 0>, 47*b53bc281SShiraz Hashim <&spics 1>; 48*b53bc281SShiraz Hashim ... 49*b53bc281SShiraz Hashim} 50