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/openbmc/linux/drivers/mtd/nand/raw/
H A Dmpc5121_nfc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2004-2008 Freescale Semiconductor, Inc.
34 /* Addresses for NFC SPARE BUFFER areas */
110 void __iomem *regs; member
127 return in_be16(prv->regs + reg); in nfc_read()
136 out_be16(prv->regs + reg, val); in nfc_write()
207 wake_up(&prv->irq_waitq); in mpc5121_nfc_irq()
221 rv = wait_event_timeout(prv->irq_waitq, in mpc5121_nfc_done()
225 dev_warn(prv->dev, in mpc5121_nfc_done()
236 u32 pagemask = chip->pagemask; in mpc5121_nfc_addr_cycle()
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H A Dmtk_nand.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
10 #include <linux/dma-mapping.h>
19 #include <linux/mtd/nand-ecc-mtk.h>
89 #define MTK_NAME "mtk-nand"
150 void __iomem *regs; member
161 * supported spare size of each IP.
162 * order should be the same with the spare size bitfiled defination of
185 return (u8 *)p + i * chip->ecc.size; in data_ptr()
197 if (i < mtk_nand->bad_mark.sec) in oob_ptr()
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H A Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
23 * bytes (also called "spare" bytes in the driver). This engine
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
39 * +-----------------------------------------
41 * +-----------------------------------------
43 * -------------------------------------------
45 * -------------------------------------------
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H A Dqcom_nandc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
207 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
210 #define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
214 ((chip)->reg_read_dma + \
215 ((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf))
244 * @bam_ce - the array of BAM command elements
245 * @cmd_sgl - sgl for NAND BAM command pipe
246 * @data_sgl - sgl for NAND BAM consumer/producer pipe
247 * @last_data_desc - last DMA desc in data channel (tx/rx).
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H A Dmxc_nand.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
27 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
28 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
29 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
30 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
31 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
32 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
33 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
34 #define NFC_V21_RSLTSPARE_AREA (host->regs + 0x10)
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/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dmxc_nand.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004-2007 Freescale Semiconductor, Inc.
14 #include <asm/arch/imx-regs.h>
23 struct mxc_nand_regs __iomem *regs; member
44 /* Define single bit Error positions in Main & Spare area */
103 while (size--) in mxc_nand_memcpy32()
117 while (max_retries-- > 0) {
119 tmp = readnfc(&host->regs->config2);
122 writenfc(tmp, &host->regs->config2);
124 tmp = readnfc(&host->ip_regs->ipc);
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H A Dfsl_ifc_spl.c1 // SPDX-License-Identifier: GPL-2.0+
38 int errors = (reg >> ((3 - bufnum % 4) * 8)) & 0xf; in check_read_ecc()
55 struct fsl_ifc regs = {(void *)CONFIG_SYS_IFC_ADDR, NULL}; in runtime_regs_address() local
58 ver = ifc_in32(&regs.gregs->ifc_rev); in runtime_regs_address()
60 regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET; in runtime_regs_address()
62 regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET; in runtime_regs_address()
64 return regs.rregs; in runtime_regs_address()
76 bufnum_end = bufnum + bufperpage - 1; in nand_wait()
79 status = ifc_in32(&ifc->ifc_nand.nand_evter_stat); in nand_wait()
89 eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]); in nand_wait()
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H A Dmxc_nand_spl.c1 // SPDX-License-Identifier: GPL-2.0+
9 * (C) Copyright 2006-2008
15 #include <asm/arch/imx-regs.h>
31 while (!(readnfc(&nfc->config2) & NFC_V1_V2_CONFIG2_INT)) in nfc_wait_ready()
35 tmp = readnfc(&nfc->config2); in nfc_wait_ready()
37 writenfc(tmp, &nfc->config2); in nfc_wait_ready()
39 while (!(readnfc(&nfc_ip->ipc) & NFC_V3_IPC_INT)) in nfc_wait_ready()
43 tmp = readnfc(&nfc_ip->ipc); in nfc_wait_ready()
45 writenfc(tmp, &nfc_ip->ipc); in nfc_wait_ready()
55 tmp = (readnfc(&nfc_ip->config2) & ~(NFC_V3_CONFIG2_SPAS_MASK | in nfc_nand_init()
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H A Domap_gpmc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
54 * omap_nand_hwcontrol - Set the address pointers corretly for the
62 int cs = info->cs; in omap_nand_hwcontrol()
70 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; in omap_nand_hwcontrol()
73 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr; in omap_nand_hwcontrol()
76 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; in omap_nand_hwcontrol()
81 writeb(cmd, this->IO_ADDR_W); in omap_nand_hwcontrol()
89 return gpmc_cfg->status & (1 << (8 + info->ws)); in omap_dev_ready()
93 * gen_true_ecc - This function will generate true ECC value, which
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H A Dfsl_ifc_nand.c1 // SPDX-License-Identifier: GPL-2.0+
48 struct fsl_ifc regs; member
56 unsigned int eccread; /* Non zero for a full-page ECC read */
61 /* 512-byte page with 4-bit ECC, 8-bit */
68 /* 512-byte page with 4-bit ECC, 16-bit */
75 /* 2048-byte page size with 4-bit ECC */
87 /* 4096-byte page size with 4-bit ECC */
103 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
127 /* 8192-byte page size with 4-bit ECC */
151 /* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,sc7180-mss-pil.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7180-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sibi Sankar <quic_sibis@quicinc.com>
19 - qcom,sc7180-mss-pil
23 - description: MSS QDSP6 registers
24 - description: RMB registers
26 reg-names:
28 - const: qdsp6
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/openbmc/linux/drivers/mtd/nand/
H A Decc-mxic.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
19 #include <linux/mtd/nand-ecc-mxic.h>
57 /* Spare Data Size */
74 /* SDMA Address of Spare Data */
80 /* Status bytes between each chunk of spare data */
89 void __iomem *regs; member
126 struct nand_ecc_engine *eng = nand->ecc.engine; in nand_to_mxic()
128 if (eng->integration == NAND_ECC_ENGINE_INTEGRATION_EXTERNAL) in nand_to_mxic()
140 if (section < 0 || section >= ctx->steps) in mxic_ecc_ooblayout_ecc()
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H A Decc-mtk.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
10 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-ecc-mtk.h>
61 void __iomem *regs; member
129 struct device *dev = ecc->dev; in mtk_ecc_wait_idle()
133 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, in mtk_ecc_wait_idle()
146 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) in mtk_ecc_irq()
149 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); in mtk_ecc_irq()
150 if (dec & ecc->sectors) { in mtk_ecc_irq()
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/openbmc/linux/drivers/soc/tegra/fuse/
H A Dfuse-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2023, NVIDIA CORPORATION. All rights reserved.
11 #include <linux/nvmem-consumer.h>
12 #include <linux/nvmem-provider.h>
52 { .compatible = "nvidia,tegra20-car", },
53 { .compatible = "nvidia,tegra30-car", },
54 { .compatible = "nvidia,tegra114-car", },
55 { .compatible = "nvidia,tegra124-car", },
56 { .compatible = "nvidia,tegra132-car", },
57 { .compatible = "nvidia,tegra210-car", },
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/openbmc/linux/arch/arm64/include/asm/
H A Dkgdb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #include <asm/debug-monitors.h>
33 * General purpose regs:
34 * r0-r30: 64 bit
38 * FPU regs:
39 * f0-f31: 128 bit
45 * Architecture Reference Manual that claimed "SPSR_ELx is a 32-bit register".
46 * and, as a result, allocated only 32-bits for the PSTATE in the remote
49 * Unfortunately "is a 32-bit register" has a very special meaning for
53 * little for people who don't spend their spare time reading ARM architecture
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/openbmc/linux/drivers/thermal/tegra/
H A Dtegra30-tsensor.c1 // SPDX-License-Identifier: GPL-2.0
9 * Copyright (C) 2021 GRATE-DRIVER project
74 void __iomem *regs; member
81 void __iomem *regs; member
95 err = reset_control_assert(ts->rst); in tegra_tsensor_hw_enable()
97 dev_err(ts->dev, "failed to assert hardware reset: %d\n", err); in tegra_tsensor_hw_enable()
101 err = clk_prepare_enable(ts->clk); in tegra_tsensor_hw_enable()
103 dev_err(ts->dev, "failed to enable clock: %d\n", err); in tegra_tsensor_hw_enable()
109 err = reset_control_deassert(ts->rst); in tegra_tsensor_hw_enable()
111 dev_err(ts->dev, "failed to deassert hardware reset: %d\n", err); in tegra_tsensor_hw_enable()
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/openbmc/linux/arch/m68k/include/asm/
H A Ddvma.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * include/asm-m68k/dma.h
16 #define DVMA_PAGE_MASK (~(DVMA_PAGE_SIZE-1))
43 #define DVMA_SIZE (DVMA_END-DVMA_START)
47 /* empirical kludge -- dvma regions only seem to work right on 0x10000
50 #define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \
51 ~(DVMA_REGION_SIZE-1))
53 /* virt <-> phys conversions */
73 #define DVMA_SIZE (DVMA_END-DVMA_START)
76 #define IOMMU_ENTRIES (IOMMU_TOTAL_ENTRIES - 0x80)
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/openbmc/linux/drivers/edac/
H A Di5400_edac.c18 * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet
21 * This Memory Controller manages DDR2 FB-DIMMs. It has 2 branches, each with
22 * 2 channels operating in lockstep no-mirror mode. Each channel can have up to
83 #define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */
88 /* Non-fatal error register */
140 * Error masks are according with Table 5-17 of i5400 datasheet
144 EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */
145 EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */
148 EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */
150 EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
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H A Di7300_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
48 * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
49 * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
106 u16 ambpresent[MAX_CHANNELS]; /* AMB present regs */
151 * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
170 * MTRx - Memory Technology Registers
192 [22] = "Non-Redundant Fast Reset Timeout",
195 [0] = "Memory Write error on non-redundant retry or "
203 [24] = "DIMM-Spare Copy Completed",
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H A Di5000_edac.c12 * Intel 5000X Chipset Memory Controller Hub (MCH) - Datasheet
102 /* Non-Retry or redundant Retry errors */
277 * MTRx - Memory Technology Registers
290 /* enables the report of miscellaneous messages as CE errors - default off */
363 u32 ferr_nf_fbd; /* First Errors Non-Fatal */
364 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */
372 * Non-Recoverable Error */
373 u16 nrecmema; /* Non-Recoverable Mem log A */
374 u32 nrecmemb; /* Non-Recoverable Mem log B */
391 pvt = mci->pvt_info; in i5000_get_error_info()
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/openbmc/linux/drivers/net/ethernet/sun/
H A Dcassini.c1 // SPDX-License-Identifier: GPL-2.0+
13 * load balancing (non-VLAN mode)
16 * page-based RX descriptor engine with separate completion rings
22 * -- driver allocates pages at a time and keeps reference counts
24 * -- the upper protocol layers assume that the header is in the skb
27 * -- driver appends the rest of the data pages as frags to skbuffs
29 * -- on page reclamation, the driver swaps the page with a spare page.
37 * TX has 4 queues. currently these queues are used in a round-robin
41 * alternatively, the queues can be configured via use of the all-purpose
49 * encrypted and non-encrypted packets, but we use them for buffering
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/openbmc/linux/arch/arm/kernel/
H A Dunwind.c1 // SPDX-License-Identifier: GPL-2.0-only
69 enum regs { enum
90 /* sign-extend to 32 bits */ \
101 * stop - 1 = last entry
125 addr_prel31 = (addr - (unsigned long)start) & 0x7fffffff; in search_index()
127 while (start < stop - 1) { in search_index()
128 const struct unwind_idx *mid = start + ((stop - start) >> 1); in search_index()
134 if (addr_prel31 - ((unsigned long)mid - (unsigned long)start) < in search_index()
135 mid->addr_offset) in search_index()
139 addr_prel31 -= ((unsigned long)mid - in search_index()
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/openbmc/linux/drivers/video/fbdev/
H A Dsm501fb.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <linux/dma-mapping.h>
39 #include <linux/sm501-regs.h>
43 static char *fb_mode = "640x480-16@60";
93 void __iomem *regs; /* remapped registers */ member
100 /* per-framebuffer private data */
119 return var->xres + var->left_margin + in h_total()
120 var->right_margin + var->hsync_len; in h_total()
125 return var->yres + var->upper_margin + in v_total()
126 var->lower_margin + var->vsync_len; in v_total()
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/openbmc/linux/drivers/mfd/
H A Dtc3589x.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2010
5 * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
6 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
22 * enum tc3589x_version - indicates the TC3589x version
38 * tc3589x_reg_read() - read a single TC3589x register
46 ret = i2c_smbus_read_byte_data(tc3589x->i2c, reg); in tc3589x_reg_read()
48 dev_err(tc3589x->dev, "failed to read reg %#x: %d\n", in tc3589x_reg_read()
56 * tc3589x_reg_write() - write a single TC3589x register
65 ret = i2c_smbus_write_byte_data(tc3589x->i2c, reg, data); in tc3589x_reg_write()
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/openbmc/linux/drivers/remoteproc/
H A Dqcom_q6v5_mss.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Qualcomm self-authenticating modem subsystem remoteproc driver
7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
13 #include <linux/dma-mapping.h>
260 static int q6v5_regulator_init(struct device *dev, struct reg_info *regs, in q6v5_regulator_init() argument
270 regs[i].reg = devm_regulator_get(dev, reg_res[i].supply); in q6v5_regulator_init()
271 if (IS_ERR(regs[i].reg)) { in q6v5_regulator_init()
272 rc = PTR_ERR(regs[i].reg); in q6v5_regulator_init()
273 if (rc != -EPROBE_DEFER) in q6v5_regulator_init()
279 regs[i].uV = reg_res[i].uV; in q6v5_regulator_init()
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