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/openbmc/linux/arch/mips/txx9/rbtx4927/
H A Dirq.c89 * RBTX4927_IRQ_IOC+00 FPCIB0 PCI-D (SouthBridge)
90 * RBTX4927_IRQ_IOC+01 FPCIB0 PCI-C (SouthBridge)
91 * RBTX4927_IRQ_IOC+02 FPCIB0 PCI-B (SouthBridge/IDE/pin=1,INTR)
92 * RBTX4927_IRQ_IOC+03 FPCIB0 PCI-A (SouthBridge/USB/pin=4)
99 * SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
100 * SouthBridge/ISA/pin=0 no pci irq used by this device
101 * SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR
103 * SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59
104 * SouthBridge/PMC/pin=0 no pci irq used by this device
108 * allowed -- SouthBridge, JP4, JP5, JP6
/openbmc/linux/drivers/mfd/
H A Drdc321x-southbridge.c3 * RDC321x MFD southbridge driver
87 .name = "RDC321x Southbridge",
96 MODULE_DESCRIPTION("RDC R-321x MFD southbridge driver");
H A Dcs5535-mfd.c163 MODULE_DESCRIPTION("MFD driver for CS5535/CS5536 southbridge's ISA PCI device");
/openbmc/linux/Documentation/hwmon/
H A Dsis5595.rst6 * Silicon Integrated Systems Corp. SiS5595 Southbridge Hardware Monitor
22 SiS southbridge has a LM78-like chip integrated on the same IC.
71 The SiS5595 southbridge has integrated hardware monitor functions. It also
H A Dvia686a.rst6 * Via VT82C686A, VT82C686B Southbridge Integrated Hardware Monitor
41 The Via 686a southbridge has integrated hardware monitor functionality.
H A Dw83627ehf.rst244 the ICH8 southbridge gets that data via PECI from the DHG, so that the
245 southbridge drives the fans. And the DHG supports SST, a one-wire serial bus.
/openbmc/qemu/hw/i2c/
H A Dsmbus_ich9.c30 #include "hw/southbridge/ich9.h"
136 * Reason: part of ICH9 southbridge, needs to be wired up by in ich9_smb_class_init()
/openbmc/u-boot/drivers/pch/
H A DKconfig7 northbridge / southbridge architecture that was previously used. The
/openbmc/linux/include/linux/mfd/
H A Drdc321x.h8 /* Offsets to be accessed in the southbridge PCI
/openbmc/linux/drivers/net/ethernet/ibm/emac/
H A DKconfig10 Axon southbridge for Cell.
/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Chassis/Control/
H A DNMISource.interface.yaml41 Via southbridge NMI.
/openbmc/phosphor-dbus-interfaces/yaml/com/intel/Control/
H A DNMISource.interface.yaml43 Via southbridge NMI.
/openbmc/linux/drivers/power/reset/
H A DKconfig158 southbridge, for example the MIPS Malta development board. The
159 southbridge SOff state is entered in response to a request to
/openbmc/u-boot/arch/x86/include/asm/arch-ivybridge/
H A Dme.h3 * From Coreboot src/southbridge/intel/bd82x6x/me.h
/openbmc/linux/Documentation/i2c/busses/
H A Di2c-ali1563.rst21 The M1563 southbridge is deceptively similar to the M1533, with a few
H A Di2c-sis96x.rst44 (drivers/pci/quirks.c) (also if southbridge detection fails)
H A Di2c-sis5595.rst11 * Silicon Integrated Systems Corp. SiS5595 Southbridge
/openbmc/qemu/tests/functional/
H A Dtest_mips64el_fuloong2e.py46 # (enough to test the fuloong2e southbridge, accessing its ISA bus)
/openbmc/qemu/hw/acpi/
H A Dich9_timer.c13 #include "hw/southbridge/ich9.h"
/openbmc/linux/drivers/cpufreq/
H A DKconfig.x86244 ICH3 or ICH4 southbridge.
256 on systems which have an Intel 440BX/ZX/MX southbridge.
/openbmc/u-boot/board/freescale/common/
H A Dcds_via.c29 * southbridge to be accessed. in mpc85xx_config_via()
/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dlpc.c3 * From coreboot southbridge/intel/bd82x6x/lpc.c
483 /* Setting up Southbridge. In the northbridge code. */ in bd82x6x_lpc_early_init()
484 debug("Setting up static southbridge registers\n"); in bd82x6x_lpc_early_init()
/openbmc/linux/drivers/i2c/busses/
H A Di2c-ali1563.c3 * i2c-ali1563.c - i2c driver for the ALi 1563 Southbridge
8 * The 1563 southbridge is deceptively similar to the 1533, with a
H A Di2c-via.c154 MODULE_DESCRIPTION("i2c for Via vt82c586b southbridge");
/openbmc/qemu/hw/pci-bridge/
H A Di82801b11.c48 #include "hw/southbridge/ich9.h"

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