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Searched full:shifter (Results 1 – 25 of 110) sorted by relevance

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/openbmc/linux/arch/microblaze/include/asm/
H A Dhash.h7 * both multiplier and barrel shifter, but omitting them is technically
10 * With just a barrel shifter, we can implement an efficient constant
24 * Without even a shifter, it's hopless; any hash function will suck.
54 * Without a barrel shifter, left shifts are implemented as in __hash_32()
/openbmc/linux/arch/arm/boot/dts/st/
H A Dste-href520-tvk.dts42 /* VMMCI level-shifter enable */
47 /* VMMCI level-shifter voltage select */
H A Dste-hrefv60plus-tvk.dts43 /* VMMCI level-shifter enable */
48 /* VMMCI level-shifter voltage select */
H A Dste-hrefv60plus-stuib.dts62 /* VMMCI level-shifter enable */
67 /* VMMCI level-shifter voltage select */
/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/
H A Ddr_ste_v1.h26 void dr_ste_v1_set_action_set(u8 *d_action, u8 hw_field, u8 shifter,
28 void dr_ste_v1_set_action_add(u8 *d_action, u8 hw_field, u8 shifter,
H A Ddr_ste.h179 u8 shifter,
184 u8 shifter,
/openbmc/linux/include/drm/display/
H A Ddrm_dp_dual_mode_helper.h76 * @DRM_LSPCON_MODE_LS: Level shifter mode of LSPCON
95 * @DRM_DP_DUAL_MODE_LSPCON: Level shifter / protocol converter
/openbmc/linux/sound/soc/tegra/
H A Dtegra20_spdif.h124 * Receiver(RX) shifter is busy receiving data.
134 * Transmitter(TX) shifter is busy transmitting data.
144 * data from CH_STA_TX_A register is loaded into the internal shifter.
147 * (b) CH_STA_TX_F register is loaded into the internal shifter.
/openbmc/qemu/include/hw/ssi/
H A Dpnv_spi_regs.h83 * Shifter states
85 * These are the same values defined for the Shifter FSM field of the
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-sck-kv-g-revA.dtso8 * SD level shifter:
131 * SD 3.0 requires level shifter and this property
132 * should be removed if the board has level shifter and
H A Dzynqmp-sck-kv-g-revB.dtso111 * SD 3.0 requires level shifter and this property
112 * should be removed if the board has level shifter and
/openbmc/u-boot/board/synopsys/iot_devkit/
H A Dconfig.mk1 …_CPPFLAGS += -mlittle-endian -mcode-density -mdiv-rem -mswap -mnorm -mmpy-option=6 -mbarrel-shifter
/openbmc/linux/drivers/gpu/drm/bridge/
H A Dti-tpd12s015.c3 * TPD12S015 HDMI ESD protection & level shifter chip driver
210 MODULE_DESCRIPTION("TPD12S015 HDMI level shifter and ESD protection driver");
H A DKconfig380 tristate "TI TPD12S015 HDMI level shifter and ESD protection"
384 Texas Instruments TPD12S015 HDMI level shifter and ESD protection
/openbmc/u-boot/include/
H A Dfsl_sec.h36 both entropy shifter and
39 entropy shifter and
42 entropy shifter, raw data
/openbmc/linux/arch/m68k/include/asm/
H A Datarihw.h78 ATARIHW_DECLARE(STND_SHIFTER); /* ST-Shifter - no base low ! */
79 ATARIHW_DECLARE(EXTD_SHIFTER); /* STe-Shifter - 24 bit address */
80 ATARIHW_DECLARE(TT_SHIFTER); /* TT-Shifter */
81 ATARIHW_DECLARE(VIDEL_SHIFTER); /* Falcon-Shifter */
154 ** Shifter
/openbmc/linux/Documentation/admin-guide/media/
H A Dcec.rst227 level-shifter that is powered off when the HPD signal is low, thus
229 the level-shifter will prevent this from functioning.
337 be connected via the level shifter to these pins: GPIO 23 and GPIO 12.
339 level shifter to these pins: GPIO 25 and GPIO 22. Monitoring the HPD and
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-controller.yaml307 Supply for the bus IO line power, such as a level shifter.
308 If the level shifter is controlled by a GPIO line, this shall
310 switching the level shifter on/off.
/openbmc/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,tpd12s015.txt1 TPD12S015 HDMI level shifter and ESD protection chip
/openbmc/linux/arch/microblaze/
H A DKconfig.platform19 on MicroBlaze systems without a barrel shifter.
/openbmc/linux/drivers/video/fbdev/omap2/omapfb/displays/
H A DKconfig17 tristate "TPD12S015 HDMI ESD protection and level shifter"
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt8183-pinctrl.yaml170 An integer describing the steps for output level shifter duty
177 An integer describing the steps for input level shifter duty cycle
H A Dmediatek,mt7622-pinctrl.yaml325 An integer describing the steps for output level shifter duty
332 An integer describing the steps for input level shifter duty cycle
H A Dmediatek,mt8365-pinctrl.yaml178 An integer describing the steps for output level shifter duty
185 An integer describing the steps for input level shifter duty cycle
/openbmc/u-boot/doc/device-tree-bindings/exynos/
H A Ddwmmc.txt36 . The above 3 values are used by the clock phase shifter.

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