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/openbmc/u-boot/drivers/clk/aspeed/
H A Dclk_ast2400.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk-uclass.h>
12 #include <dt-bindings/clock/ast2400-clock.h>
13 #include <dt-bindings/reset/ast2400-reset.h>
19 * For H-PLL and M-PLL the formula is
21 * M - Numerator
22 * N - Denumerator
23 * P - Post Divider
26 * D-PLL and D2-PLL have extra divider (OD + 1), which is not
37 extern u32 ast2400_get_clkin(struct ast2400_scu *scu) in ast2400_get_clkin() argument
[all …]
H A Dclk_ast2500.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <clk-uclass.h>
15 #include <dt-bindings/clock/ast2500-clock.h>
16 #include <dt-bindings/reset/ast2500-reset.h>
36 * For H-PLL and M-PLL the formula is
38 * M - Numerator
39 * N - Denumerator
40 * P - Post Divider
43 * D-PLL and D2-PLL have extra divider (OD + 1), which is not
52 extern u32 ast2500_get_clkin(struct ast2500_scu *scu) in ast2500_get_clkin() argument
[all …]
H A Dclk_ast2600.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <clk-uclass.h>
15 #include <dt-bindings/clock/ast2600-clock.h>
16 #include <dt-bindings/reset/ast2600-reset.h>
19 * SCU 80 & 90 clock stop control for MAC controllers
87 * SCU 320 & 330 Frequency counters
134 * For H-PLL and M-PLL the formula is
136 * M - Numerator
137 * N - Denumerator
138 * P - Post Divider
[all …]
/openbmc/linux/drivers/clk/imx/
H A Dclk-scu.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2021 NXP
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <linux/arm-smccc.h>
10 #include <linux/clk-provider.h>
18 #include "clk-scu.h"
42 * struct clk_scu - Description of one SCU clock
44 * @rsrc_id: resource ID of this SCU clock
60 * struct clk_gpr_scu - Description of one SCU GPR clock
62 * @rsrc_id: resource ID of this SCU clock
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 mxc-clk-objs += clk.o
4 mxc-clk-objs += clk-busy.o
5 mxc-clk-objs += clk-composite-7ulp.o
6 mxc-clk-objs += clk-composite-8m.o
7 mxc-clk-objs += clk-composite-93.o
8 mxc-clk-objs += clk-fracn-gppll.o
9 mxc-clk-objs += clk-cpu.o
10 mxc-clk-objs += clk-divider-gate.o
11 mxc-clk-objs += clk-fixup-div.o
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dfsl,scu-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX SCU Client Device Node - Clock Controller Based on SCU Message Protocol
10 - Abel Vesa <abel.vesa@nxp.com>
12 description: i.MX SCU Client Device Node
13 Client nodes are maintained as children of the relevant IMX-SCU device node.
15 (Documentation/devicetree/bindings/clock/clock-bindings.txt)
18 include/dt-bindings/clock/imx8qxp-clock.h
[all …]
H A Dairoha,en7523-scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/airoha,en7523-scu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felix Fietkau <nbd@nbd.name>
11 - John Crispin <nbd@nbd.name>
25 [1]: <include/dt-bindings/clock/en7523-clk.h>.
32 - const: airoha,en7523-scu
37 "#clock-cells":
44 - compatible
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/openbmc/linux/Documentation/devicetree/bindings/firmware/
H A Dfsl,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/fsl,scu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
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/openbmc/linux/drivers/gpu/drm/aspeed/
H A Daspeed_gfx_drv.c1 // SPDX-License-Identifier: GPL-2.0+
4 #include <linux/clk.h>
5 #include <linux/dma-mapping.h>
61 u32 dac_reg; /* DAC register in SCU */
63 u32 vga_scratch_reg; /* VGA scratch register in SCU */
93 { .compatible = "aspeed,ast2400-gfx", .data = &ast2400_config },
94 { .compatible = "aspeed,ast2500-gfx", .data = &ast2500_config },
95 { .compatible = "aspeed,ast2600-gfx", .data = &ast2600_config },
114 drm->mode_config.min_width = 0; in aspeed_gfx_setup_mode_config()
115 drm->mode_config.min_height = 0; in aspeed_gfx_setup_mode_config()
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/openbmc/linux/drivers/soc/aspeed/
H A Daspeed-lpc-ctrl.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk.h>
17 #include <linux/aspeed-lpc-ctrl.h>
19 #define DEVICE_NAME "aspeed-lpc-ctrl"
34 struct clk *clk; member
40 struct regmap *scu; member
45 return container_of(file->private_data, struct aspeed_lpc_ctrl, in file_aspeed_lpc_ctrl()
52 unsigned long vsize = vma->vm_end - vma->vm_start; in aspeed_lpc_ctrl_mmap()
53 pgprot_t prot = vma->vm_page_prot; in aspeed_lpc_ctrl_mmap()
55 if (vma->vm_pgoff + vma_pages(vma) > lpc_ctrl->mem_size >> PAGE_SHIFT) in aspeed_lpc_ctrl_mmap()
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/openbmc/linux/Documentation/devicetree/bindings/arm/apm/
H A Dscu.txt1 APM X-GENE SoC series SCU Registers
7 - compatible : should contain two values. First value must be:
8 - "apm,xgene-scu"
11 - reg : offset and length of the register set.
14 scu: system-clk-controller@17000000 {
15 compatible = "apm,xgene-scu","syscon";
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8dxl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx8-clock.h>
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/pinctrl/pads-imx8dxl.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
[all …]
H A Dimx8qxp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2020 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/clock/imx8-lpcg.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
15 #include <dt-bindings/thermal/thermal.h>
[all …]
H A Dimx8qm.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/pads-imx8qm.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
[all …]
H A Dimx8-ss-dma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 dma_ipg_clk: clock-dma-ipg {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
[all …]
/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-lpc18xx.c2 * Pinctrl driver for NXP LPC18xx/LPC43xx System Control Unit (SCU)
12 #include <linux/clk.h>
18 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
26 /* LPC18XX SCU analog function registers */
32 /* LPC18XX SCU pin register definitions */
54 /* LPC18XX SCU pin interrupt select registers */
68 TYPE_ND, /* Normal-drive */
69 TYPE_HD, /* High-drive */
70 TYPE_HS, /* High-speed */
[all …]
/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Dpads-imx8qxp.h1 /* SPDX-License-Identifier: GPL-2.0+ */
18 #define SC_P_EMMC0_CLK 9 /* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4…
27 … 18 /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */
39 #define SC_P_USDHC1_CLK 30 /* CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.I…
50 #define SC_P_ENET0_RGMII_TXD2 41 /* CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NA…
53 … 44 /* CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */
65 #define SC_P_ESAI0_FST 56 /* ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01…
85 … 76 /* ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSI…
87 … 78 /* ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */
88 … 79 /* ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dfsl,flexcan.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
11 - Marc Kleine-Budde <mkl@pengutronix.de>
14 - $ref: can-controller.yaml#
19 - enum:
20 - fsl,imx93-flexcan
21 - fsl,imx8qm-flexcan
22 - fsl,imx8mp-flexcan
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dast2600-u-boot.dtsi1 #include <dt-bindings/clock/ast2600-clock.h>
2 #include <dt-bindings/reset/ast2600-reset.h>
7 scu: clock-controller@1e6e2000 { label
8 compatible = "aspeed,ast2600-scu";
10 u-boot,dm-pre-reloc;
11 #clock-cells = <1>;
12 #reset-cells = <1>;
13 uart-clk-source = <0x0>; /* uart clock source selection: 0: uxclk 1: huxclk*/
16 rst: reset-controller {
17 u-boot,dm-pre-reloc;
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/openbmc/u-boot/drivers/clk/renesas/
H A Dr8a7791-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2015-2017 Glider bvba
10 * Based on clk-rcar-gen2.c
15 #include <clk-uclass.h>
18 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen2-cpg.h"
96 DEF_MOD("2d-dmac", 115, R8A7791_CLK_ZS),
97 DEF_MOD("fdp1-1", 118, R8A7791_CLK_ZS),
98 DEF_MOD("fdp1-0", 119, R8A7791_CLK_ZS),
[all …]
H A Dr8a7790-cpg-mssr.c6 * Based on clk-rcar-gen2.c
16 #include <clk-uclass.h>
19 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen2-cpg.h"
103 DEF_MOD("2d-dmac", 115, R8A7790_CLK_ZS),
104 DEF_MOD("fdp1-2", 117, R8A7790_CLK_ZS),
105 DEF_MOD("fdp1-1", 118, R8A7790_CLK_ZS),
106 DEF_MOD("fdp1-0", 119, R8A7790_CLK_ZS),
113 DEF_MOD("vsp1-rt", 130, R8A7790_CLK_ZS),
[all …]
H A Dr8a7794-cpg-mssr.c6 * Based on clk-rcar-gen2.c
16 #include <clk-uclass.h>
19 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen2-cpg.h"
95 DEF_MOD("2d-dmac", 115, R8A7794_CLK_ZS),
96 DEF_MOD("fdp1-0", 119, R8A7794_CLK_ZS),
102 DEF_MOD("vsp1-sy", 131, R8A7794_CLK_ZS),
111 DEF_MOD("sys-dmac1", 218, R8A7794_CLK_ZS),
112 DEF_MOD("sys-dmac0", 219, R8A7794_CLK_ZS),
[all …]
/openbmc/u-boot/drivers/ram/aspeed/
H A Dsdram_ast2500.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2012-2020 ASPEED Technology Inc.
9 #include <clk.h>
20 #include <dt-bindings/clock/ast2500-clock.h>
22 /* in order to speed up DRAM init time, write pre-defined values to registers
26 /* bit-field of m_pll_param */
84 struct clk ddr_clk;
86 struct ast2500_scu *scu; member
93 writel(0, &phy->phy[2]); in ast2500_sdrammc_init_phy()
94 writel(0, &phy->phy[6]); in ast2500_sdrammc_init_phy()
[all …]
/openbmc/linux/drivers/clk/
H A Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
48 /* clk rst name parent flags */
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
[all …]
/openbmc/linux/drivers/clk/renesas/
H A Dr8a7795-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 * Based on clk-rcar-gen3.c
16 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
133 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
134 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
149 DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
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