| /openbmc/linux/Documentation/devicetree/bindings/ata/ |
| H A D | sata-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/sata-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Serial AT attachment (SATA) controllers
10 - Linus Walleij <linus.walleij@linaro.org>
14 AT attachment (SATA) storage devices. It doesn't constitute a device tree
18 The SATA controller-specific device tree bindings are responsible for
23 pattern: "^sata(@.*)?$"
25 Specifies the host controller node. SATA host controller nodes are named
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| H A D | ahci-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <dlemoal@kernel.org>
14 This document defines device tree properties for a common AHCI SATA
18 document doesn't constitute a DT-node binding by itself but merely
19 defines a set of common properties for the AHCI-compatible devices.
24 - $ref: sata-common.yaml#
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| H A D | rockchip,dwc-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller for Rockchip devices
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller found in Rockchip
22 - rockchip,rk3568-dwc-ahci
23 - rockchip,rk3588-dwc-ahci
25 - compatible
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| H A D | ahci-platform.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AHCI SATA Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
11 Each SATA controller should have its own node.
13 It is possible, but not required, to represent each port as a sub-node.
14 It allows to enable each port independently when dealing with multiple
18 - Hans de Goede <hdegoede@redhat.com>
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| H A D | snps,dwc-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller.
20 - snps,dwc-ahci
21 - snps,spear-ahci
23 - compatible
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| H A D | baikal,bt1-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 SoC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 AHCI SATA controller embedded into the Baikal-T1 SoC is based on the
14 DWC AHCI SATA v4.10a IP-core.
17 - $ref: snps,dwc-ahci-common.yaml#
21 const: baikal,bt1-ahci
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| H A D | snps,dwc-ahci-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller properties
10 - Serge Semin <fancer.lancer@gmail.com>
19 - $ref: ahci-common.yaml#
30 Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock,
31 PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
36 clock-names:
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| H A D | sata_highbank.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda AHCI SATA Controller
10 The Calxeda SATA controller mostly conforms to the AHCI interface
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-ahci
27 dma-coherent: true
29 calxeda,pre-clocks:
35 calxeda,post-clocks:
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| H A D | faraday,ftide010.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
15 platform. The controller can do PIO modes 0 through 4, Multi-word DMA
19 SATA bridge in order to support SATA. This is why a phandle to that
22 The timing properties are unique per-SoC, not per-board.
27 - const: faraday,ftide010
28 - items:
29 - const: cortina,gemini-pata
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| /openbmc/u-boot/drivers/ata/ |
| H A D | sata_sil.c | 1 // SPDX-License-Identifier: GPL-2.0+
14 #include <sata.h>
16 #include <sata.h>
35 printf("fis_type: %02x\n", s->fis_type); in sil_sata_dump_fis()
36 printf("pm_port_i: %02x\n", s->pm_port_i); in sil_sata_dump_fis()
37 printf("status: %02x\n", s->status); in sil_sata_dump_fis()
38 printf("error: %02x\n", s->error); in sil_sata_dump_fis()
39 printf("lba_low: %02x\n", s->lba_low); in sil_sata_dump_fis()
40 printf("lba_mid: %02x\n", s->lba_mid); in sil_sata_dump_fis()
41 printf("lba_high: %02x\n", s->lba_high); in sil_sata_dump_fis()
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| H A D | mvsata_ide.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Written-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
19 /* SATA port registers */
42 * - to compile at all, we need CONFIG_SYS_ATA_BASE_ADDR.
43 * - for ide_preinit to make sense, we need at least one of
45 * - for ide_preinit to be called, we need CONFIG_IDE_PREINIT.
85 * If/when standard negative codes are implemented in U-Boot, then these
91 #define MVSATA_STATUS_TIMEOUT -1
94 * Registers for SATA MBUS memory windows
101 * Initialize SATA memory windows for Armada XP
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| /openbmc/u-boot/doc/device-tree-bindings/ata/ |
| H A D | intel-sata.txt | 1 Intel Pantherpoint SATA Device Binding
5 SATA device is as follows:
8 - compatible = "intel,pantherpoint-ahci"
9 - intel,sata-mode : string, one of:
12 "plain-ide" : Use plain IDE mode
13 - intel,sata-port-map : Which SATA ports are enabled, bit 0=enable first port,
14 bit 1=enable second port, etc.
15 - intel,sata-port0-gen3-tx : Value for the IOBP_SP0G3IR register
16 - intel,sata-port1-gen3-tx : Value for the IOBP_SP1G3IR register
19 -------
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| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | phy-miphy365x.txt | 5 for SATA and PCIe.
8 - compatible : Should be "st,miphy365x-phy"
9 - st,syscfg : Phandle / integer array property. Phandle of sysconfig group
11 an entry for each port sub-node, specifying the control
14 Required nodes : A sub-node is required for each channel the controller
16 'reg' and 'reg-names' properties are used inside these
20 Required properties (port (child) node):
21 - #phy-cells : Should be 1 (See second example)
22 Cell after port phandle is device type from:
23 - PHY_TYPE_SATA
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| H A D | brcm,sata-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <f.fainelli@gmail.com>
14 pattern: "^sata[-|_]phy(@.*)?$"
18 - items:
19 - enum:
20 - brcm,bcm7216-sata-phy
21 - brcm,bcm7425-sata-phy
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| H A D | phy-miphy28lp.txt | 5 for SATA, PCIe or USB3.
8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
10 which contain the SATA, PCIe or USB3 mode setting bits.
12 Required nodes : A sub-node is required for each channel the controller
14 'reg' and 'reg-names' properties are used inside these
18 Required properties (port (child) node):
19 - #phy-cells : Should be 1 (See second example)
20 Cell after port phandle is device type from:
21 - PHY_TYPE_SATA
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| /openbmc/linux/drivers/scsi/mvsas/ |
| H A D | mv_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
31 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
32 /* software requires power-of-2
40 MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */
44 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
77 INT_SAS_SATA = (1U << 0), /* SAS/SATA event */
79 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
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| /openbmc/u-boot/include/ |
| H A D | ahci.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
39 #define HOST_RESET (1 << 0) /* reset controller; self-clear */
43 /* Registers for each SATA port */
50 #define PORT_CMD 0x18 /* port command */
54 #define PORT_SCR 0x28 /* SATA phy register block */
55 #define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
56 #define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
57 #define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
58 #define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
70 #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
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| /openbmc/linux/drivers/phy/tegra/ |
| H A D | xusb-tegra124.c | 1 // SPDX-License-Identifier: GPL-2.0-only
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
259 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_disable()
261 if (WARN_ON(padctl->enable == 0)) in tegra124_xusb_padctl_disable()
264 if (--padctl->enable > 0) in tegra124_xusb_padctl_disable()
284 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_disable()
291 struct tegra_xusb_usb3_port *port; in tegra124_usb3_save_context() local
295 port = tegra_xusb_find_usb3_port(padctl, index); in tegra124_usb3_save_context()
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| H A D | xusb-tegra210.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
27 ((x) ? (11 + ((x) - 1) * 6) : 0)
443 { 3, "sata", 0 },
451 for (map = tegra210_usb3_map; map->type; map++) { in tegra210_usb3_lane_map()
452 if (map->index == lane->index && in tegra210_usb3_lane_map()
453 strcmp(map->type, lane->pad->soc->name) == 0) { in tegra210_usb3_lane_map()
454 dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n", in tegra210_usb3_lane_map()
455 lane->pad->soc->lanes[lane->index].name, map->port); in tegra210_usb3_lane_map()
456 return map->port; in tegra210_usb3_lane_map()
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| /openbmc/linux/drivers/scsi/aic94xx/ |
| H A D | aic94xx_dev.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Aic94xx SAS/SATA DDB management
16 #define FIND_FREE_DDB(_ha) find_first_zero_bit((_ha)->hw_prof.ddb_bitmap, \
17 (_ha)->hw_prof.max_ddbs)
18 #define SET_DDB(_ddb, _ha) set_bit(_ddb, (_ha)->hw_prof.ddb_bitmap)
19 #define CLEAR_DDB(_ddb, _ha) clear_bit(_ddb, (_ha)->hw_prof.ddb_bitmap)
26 if (ddb >= asd_ha->hw_prof.max_ddbs) { in asd_get_ddb()
27 ddb = -ENOMEM; in asd_get_ddb()
67 struct asd_ha_struct *asd_ha = dev->port->ha->lldd_ha; in asd_set_ddb_type()
68 int ddb = (int) (unsigned long) dev->lldd_dev; in asd_set_ddb_type()
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | mvebu-gated-clock.txt | 12 -----------------------------------
20 15 sata0 SATA Host 0
25 30 sata1 SATA Host 0
29 -----------------------------------
37 14 sata0_link SATA 0 Link
38 15 sata0_core SATA 0 Core
43 20 sata1_link SATA 1 Link
44 21 sata1_core SATA 1 Core
49 28 crypto0_enc Cryptographic Unit Port 0 Encryption
50 29 crypto0_core Cryptographic Unit Port 0 Core
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| /openbmc/linux/drivers/phy/samsung/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 tristate "Exynos SoC series Display Port PHY driver"
12 Support for Display Port PHY found on Samsung Exynos SoCs.
15 tristate "S5P/Exynos SoC series MIPI CSI-2/DSI PHY driver"
21 Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
77 are available - device and host.
93 tristate "Exynos5250 Sata SerDes/PHY driver"
102 Enable this to support SATA SerDes/Phy found on Samsung's
103 Exynos5250 based SoCs.This SerDes/Phy supports SATA 1.5 Gb/s,
104 SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds. It supports one SATA host
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| /openbmc/u-boot/arch/x86/cpu/broadwell/ |
| H A D | sata.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * From coreboot src/soc/intel/broadwell/sata.c
26 * SATA DEVSLP Mux
27 * 0 = port 0 DEVSLP on DEVSLP0/GPIO33
28 * 1 = port 3 DEVSLP on DEVSLP0/GPIO33
46 int port; in broadwell_sata_init() local
48 debug("SATA: Initializing controller in AHCI mode.\n"); in broadwell_sata_init()
54 /* for AHCI, Port Enable is managed in memory mapped space */ in broadwell_sata_init()
57 reg16 |= 0x8000 | plat->port_map; in broadwell_sata_init()
73 /* SATA Initialization register */ in broadwell_sata_init()
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| /openbmc/linux/drivers/phy/broadcom/ |
| H A D | phy-brcm-sata.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
27 /* The older SATA PHY registers duplicated per port registers within the map,
28 * rather than having a separate map per port.
194 static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port) in brcm_sata_ctrl_base() argument
196 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_ctrl_base()
199 switch (priv->version) { in brcm_sata_ctrl_base()
204 dev_err(priv->dev, "invalid phy version\n"); in brcm_sata_ctrl_base()
208 return priv->ctrl_base + (port->portnum * size); in brcm_sata_ctrl_base()
211 static void brcm_sata_phy_wr(struct brcm_sata_port *port, u32 bank, in brcm_sata_phy_wr() argument
214 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_phy_wr()
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| /openbmc/linux/drivers/scsi/isci/ |
| H A D | probe_roms.h | 7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
102 * by phys in the supplied port.
103 * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
104 * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
105 * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
197 /* Allowed PORT configuration modes APC Automatic PORT configuration mode is
199 * for any PORT. i.e. There are no phys assigned to any of the ports at start.
200 * MPC Manual PORT configuration mode is defined by the OEM configuration
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