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/openbmc/linux/drivers/gpu/drm/omapdrm/
H A Dtcm-sita.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
26 * stride slots in a row
29 unsigned long *map, u16 stride) in free_slots() argument
33 for (i = 0; i < h; i++, pos += stride) in free_slots()
50 *pos = num_bits - w; in r2l_b2t_1d()
55 if (bit - *pos >= w) { in r2l_b2t_1d()
62 search_count = num_bits - bit + w; in r2l_b2t_1d()
63 *pos = bit - w; in r2l_b2t_1d()
66 return (area_found) ? 0 : -ENOMEM; in r2l_b2t_1d()
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H A Domap_gem.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
7 #include <linux/dma-mapping.h>
23 /* note: we use upper 8 bits of flags for driver-internal flags: */
47 * - buffers allocated through the DMA mapping API (with the
50 * - buffers imported from dmabuf (with the OMAP_BO_MEM_DMABUF flag set)
51 * if they are physically contiguous (when sgt->orig_nents == 1)
53 * - buffers mapped through the TILER when pin_cnt is not zero, in which
103 * regions in each of the 2d containers to use as a user-GART where we
104 * can create a second page-aligned mapping of parts of the buffer
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/openbmc/linux/drivers/gpu/ipu-v3/
H A Dipu-image-convert.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012-2016 Mentor Graphics Inc.
9 #include <linux/dma-mapping.h>
12 #include <video/imx-ipu-image-convert.h>
14 #include "ipu-prv.h"
28 * tile (but taking care to pass the full frame stride length to
29 * the DMA channel's parameter memory!). IDMA double-buffering is used
30 * to convert each tile back-to-back when possible (see note below
36 * +---------+-----+
37 * +-----+---+ | A | B |
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/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3288.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
12 #include <dt-structs.h>
59 /* row col,bw */
102 rk_clrsetreg(&cru->cru_softrst_con[10], in ddr_reset()
115 rk_clrsetreg(&cru->cru_softrst_con[10], in ddr_phy_ctl_reset()
127 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
129 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
132 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
134 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
150 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
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H A Dsdram_rk3399.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * (C) Copyright 2016-2017 Rockchip Inc.
11 #include <dt-structs.h>
83 u32 *denali_phy = ddr_publ_regs->denali_phy; in phy_dll_bypass_set()
115 &sdram_params->ch[channel]; in set_memory_map()
116 u32 *denali_ctl = chan->pctl->denali_ctl; in set_memory_map()
117 u32 *denali_pi = chan->pi->denali_pi; in set_memory_map()
120 u32 row; in set_memory_map() local
122 /* Get row number from ddrconfig setting */ in set_memory_map()
123 if (sdram_ch->ddrconfig < 2 || sdram_ch->ddrconfig == 4) in set_memory_map()
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/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
20 synthesis time. As a result, many of the device-tree bindings are meant to
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
32 - xylon,logicvc-3.02.a-display
33 - xylon,logicvc-4.01.a-display
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/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_frontend.h1 // SPDX-License-Identifier: GPL-2.0+
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
41 * In tiled mode, the stride is defined as the distance between the start of the
45 * Tiles are represented in row-major order, thus the end line of current tile
47 * 32-bit-aligned-width * 32 and the distance is:
48 * 32 * (32-bit-aligned-width - 31).
50 #define SUN4I_FRONTEND_LINESTRD_TILED(stride) (((stride) - 31) * 32) argument
79 #define SUN4I_FRONTEND_INSIZE(h, w) ((((h) - 1) << 16) | (((w) - 1)))
82 #define SUN4I_FRONTEND_OUTSIZE(h, w) ((((h) - 1) << 16) | (((w) - 1)))
/openbmc/u-boot/arch/arm/include/asm/arch-tegra20/
H A Ddisplay.h1 /* SPDX-License-Identifier: GPL-2.0+ */
10 #include <asm/arch-tegra/dc.h>
21 unsigned stride; /* Number of bytes per line */ member
23 unsigned out_y; /* Top edge of output window (row) */
/openbmc/linux/include/xen/interface/io/
H A Dfbif.h1 /* SPDX-License-Identifier: MIT */
3 * fbif.h -- Xen virtual frame buffer device
12 /* Out events (frontend -> backend) */
22 * Capable frontend sets feature-update in xenstore.
23 * Backend requests it by setting request-update in xenstore.
37 * Capable backend sets feature-resize in xenstore.
45 int32_t stride; /* stride in bytes */ member
59 /* In events (backend -> frontend) */
97 uint32_t line_length; /* length of a row of pixels (in bytes) */
/openbmc/linux/drivers/staging/media/atomisp/pci/isp/kernels/sdis/sdis_2/
H A Dia_css_sdis2.host.c1 // SPDX-License-Identifier: GPL-2.0
41 unsigned int aligned_width = from->grid.aligned_width * in ia_css_sdis2_horicoef_vmem_encode()
42 from->grid.bqs_per_grid_cell; in ia_css_sdis2_horicoef_vmem_encode()
43 unsigned int width = from->grid.num_hor_coefs; in ia_css_sdis2_horicoef_vmem_encode()
44 int padding = aligned_width - width; in ia_css_sdis2_horicoef_vmem_encode()
45 unsigned int stride = size / IA_CSS_DVS2_NUM_COEF_TYPES / sizeof(short); in ia_css_sdis2_horicoef_vmem_encode() local
55 fill_row(&private[0 * stride], from->hor_coefs.odd_real, width, padding); in ia_css_sdis2_horicoef_vmem_encode()
56 fill_row(&private[1 * stride], from->hor_coefs.odd_imag, width, padding); in ia_css_sdis2_horicoef_vmem_encode()
57 fill_row(&private[2 * stride], from->hor_coefs.even_real, width, padding); in ia_css_sdis2_horicoef_vmem_encode()
58 fill_row(&private[3 * stride], from->hor_coefs.even_imag, width, padding); in ia_css_sdis2_horicoef_vmem_encode()
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/openbmc/linux/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_mman.c2 * SPDX-License-Identifier: MIT
33 unsigned int stride; member
41 return (offset & BIT_ULL(bit)) >> (bit - 6); in swizzle_bit()
48 if (tile->tiling == I915_TILING_NONE) in tiled_offset()
51 y = div64_u64_rem(v, tile->stride, &x); in tiled_offset()
52 v = div64_u64_rem(y, tile->height, &y) * tile->stride * tile->height; in tiled_offset()
54 if (tile->tiling == I915_TILING_X) { in tiled_offset()
55 v += y * tile->width; in tiled_offset()
56 v += div64_u64_rem(x, tile->width, &x) << tile->size; in tiled_offset()
58 } else if (tile->width == 128) { in tiled_offset()
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/openbmc/qemu/include/hw/xen/interface/io/
H A Dfbif.h1 /* SPDX-License-Identifier: MIT */
3 * fbif.h -- Xen virtual frame buffer device
12 /* Out events (frontend -> backend) */
22 * Capable frontend sets feature-update in xenstore.
23 * Backend requests it by setting request-update in xenstore.
38 * Capable backend sets feature-resize in xenstore.
47 int32_t stride; /* stride in bytes */ member
62 /* In events (backend -> frontend) */
71 * refresh. Frontends that keep the framebuffer constantly up-to-date
121 uint32_t line_length; /* the length of a row of pixels (in bytes) */
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/openbmc/linux/drivers/nvmem/
H A Dbcm-ocotp.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/nvmem-provider.h>
45 #define OTPC_CMD_MASK (BIT(OTPC_COMMAND_COMMAND_WIDTH) - 1)
46 #define OTPC_ADDR_MASK (BIT(OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH) - 1)
52 /* 128 bit row / 4 words support. */
54 /* 128 bit row / 4 words support. */
114 return -EAGAIN; in poll_cpu_status()
157 u32 address = offset / priv->config->word_size; in bcm_otpc_read()
161 set_command(priv->base, OTPC_CMD_READ); in bcm_otpc_read()
162 set_cpu_address(priv->base, address++); in bcm_otpc_read()
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/openbmc/u-boot/arch/x86/cpu/quark/
H A Dmrc.c1 // SPDX-License-Identifier: Intel
13 * These functions are generic and should work for any Quark-based board.
20 * 02) Set up Memory Manager buffer as pass-through (POR)
21 * 03) Set Channel Interleaving Mode and Channel Stride to the most aggressive
30 * 11) Set Channel Interleaving Mode and Channel Stride to the desired settings
80 mrc_params->status = MRC_SUCCESS; in mrc_adjust_params()
82 dram_width = mrc_params->dram_width; in mrc_adjust_params()
83 rank_enables = mrc_params->rank_enables; in mrc_adjust_params()
84 channel_width = mrc_params->channel_width; in mrc_adjust_params()
92 mrc_params->board_id = 2; /* select x8 layout */ in mrc_adjust_params()
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/openbmc/qemu/tests/tcg/hexagon/
H A Dhvx_histogram_row.S21 * int stride, => r1
64 r10 = add(r0, r1) /* R10 = &src[2 * stride] */
85 if (p1) jump .skip /* if (width % VLEN == 0) done with current row */
92 { r0 = r10 /* R0 = &src[(i + 1) * stride] */
93 r10 = add(r10, r1) /* R10 = &src[(i + 2) * stride] */
246 v1.tmp = vmem(r4 + #0) /* update hist[0-31] */
255 v1.tmp = vmem(r4 + #0) /* update hist[32-63] */
264 v1.tmp = vmem(r4 + #0) /* update hist[64-95] */
269 v1.tmp = vmem(r4 + #0) /* update hist[96-127] */
275 v1.tmp = vmem(r4 + #0) /* update hist[128-159] */
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/openbmc/linux/drivers/gpu/drm/logicvc/
H A Dlogicvc_of.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-2022 Bootlin
14 { "lvds-4bits", LOGICVC_DISPLAY_INTERFACE_LVDS_4BITS },
15 { "lvds-3bits", LOGICVC_DISPLAY_INTERFACE_LVDS_3BITS },
40 .name = "xylon,display-interface",
48 .name = "xylon,display-colorspace",
56 .name = "xylon,display-depth",
60 .name = "xylon,row-stride",
67 .name = "xylon,background-layer",
71 .name = "xylon,layers-configurable",
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/openbmc/linux/drivers/thermal/intel/
H A Dintel_hfi.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
22 #define pr_fmt(fmt) "intel-hfi: " fmt
33 #include <linux/percpu-defs.h>
79 * struct hfi_cpu_data - HFI capabilities per CPU
92 * struct hfi_hdr - Header of the HFI table
104 * struct hfi_instance - Representation of an HFI instance (i.e., a table)
133 * struct hfi_features - Supported HFI features
135 * @cpu_stride: Stride size to locate the capability data of a logical
136 * processor within the table (i.e., row stride)
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/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-yuv-planar.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. planar-yuv:
12 - Semi-planar formats use two planes. The first plane is the luma plane and
16 - Fully planar formats use three planes to store the Y, Cb and Cr components
20 tiled. Padding may be supported at the end of the lines, and the line stride of
21 the chroma planes may be constrained by the line stride of the luma plane.
26 and applications that support the multi-planar API, described in
27 :ref:`planar-apis`. Unless explicitly documented as supporting non-contiguous
31 Semi-Planar YUV Formats
42 subsampling, the chroma line stride (in bytes) is thus equal to twice the luma
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/openbmc/linux/drivers/net/ethernet/sfc/
H A Dmae.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2020-2022 Xilinx Inc.
29 return -EINVAL; in efx_mae_allocate_mport()
31 return -EINVAL; in efx_mae_allocate_mport()
42 return -EIO; in efx_mae_allocate_mport()
64 MAE_MPORT_SELECTOR_PPORT_ID, efx->port_num); in efx_mae_mport_wire()
115 return -EIO; in efx_mae_fw_lookup_mport()
131 efx->net_dev->mtu); in efx_mae_start_counters()
140 return -EIO; in efx_mae_start_counters()
143 netif_dbg(efx, drv, efx->net_dev, in efx_mae_start_counters()
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/openbmc/u-boot/drivers/video/
H A Dmx3fb.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
19 /* this might need panel specific set-up as-well */
22 /* -------------- controller specific stuff -------------- */
100 /* IPU_CONF and its bits already defined in imx-regs.h */
352 * sdc_init_panel() - initialize a synchronous LCD panel.
371 return -EACCES; in sdc_init_panel()
374 reg = width + mode->left_margin + mode->right_margin - 1; in sdc_init_panel()
379 reg = ((mode->hsync_len - 1) << 26) | (reg << 16); in sdc_init_panel()
382 reg = height + mode->upper_margin + mode->lower_margin - 1; in sdc_init_panel()
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/openbmc/qemu/include/standard-headers/drm/
H A Ddrm_fourcc.h38 * further describe the buffer's format - for example tiling or compression.
41 * ----------------
55 * vendor-namespaced, and as such the relationship between a fourcc code and a
57 * may preserve meaning - such as number of planes - from the fourcc code,
63 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
75 * - Kernel and user-space drivers: for drivers it's important that modifiers
79 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
92 * -----------------------
97 * upstream in-kernel or open source userspace user does not apply.
221 * IEEE 754-2008 binary16 half-precision float
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/openbmc/linux/include/uapi/drm/
H A Ddrm_fourcc.h39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
93 * -----------------------
98 * upstream in-kernel or open source userspace user does not apply.
222 * IEEE 754-2008 binary16 half-precision float
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/openbmc/linux/drivers/gpu/drm/vmwgfx/
H A Dvmw_surface_cache.h3 * SPDX-License-Identifier: GPL-2.0 OR MIT
37 return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp; in clamped_umul32()
41 * vmw_surface_get_desc - Look up the appropriate SVGA3dSurfaceDesc for the
54 * vmw_surface_get_mip_size - Given a base level size and the mip level,
74 block_size->width = __KERNEL_DIV_ROUND_UP(pixel_size->width, in vmw_surface_get_size_in_blocks()
75 desc->blockSize.width); in vmw_surface_get_size_in_blocks()
76 block_size->height = __KERNEL_DIV_ROUND_UP(pixel_size->height, in vmw_surface_get_size_in_blocks()
77 desc->blockSize.height); in vmw_surface_get_size_in_blocks()
78 block_size->depth = __KERNEL_DIV_ROUND_UP(pixel_size->depth, in vmw_surface_get_size_in_blocks()
79 desc->blockSize.depth); in vmw_surface_get_size_in_blocks()
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/openbmc/linux/drivers/staging/media/atomisp/pci/isp/kernels/dvs/dvs_1.0/
H A Dia_css_dvs.host.c1 // SPDX-License-Identifier: GPL-2.0
43 to->num_horizontal_blocks = in ia_css_dvs_config()
44 DVS_NUM_BLOCKS_X(from->info->res.width); in ia_css_dvs_config()
45 to->num_vertical_blocks = in ia_css_dvs_config()
46 DVS_NUM_BLOCKS_Y(from->info->res.height); in ia_css_dvs_config()
94 assert(gdc_warp_table->address); in convert_coords_to_ispparams()
96 ptr = (struct gdc_warp_param_mem_s *)gdc_warp_table->address; in convert_coords_to_ispparams()
101 xbuff = config->xcoords_y; in convert_coords_to_ispparams()
102 ybuff = config->ycoords_y; in convert_coords_to_ispparams()
103 width = config->width_y; in convert_coords_to_ispparams()
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/openbmc/linux/drivers/staging/media/ipu3/
H A Dipu3-abi.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include "include/uapi/intel-ipu3.h"
106 #define IMGU_REG_L1_PHYS (IMGU_REG_BASE + 0x304) /* 27-bit pfn */
121 /* For each definition there is signal pair : valid [bit 0]- accept [bit 1] */
151 #define IMGU_GP_STRMON_STAT_MOD_PORT_S2V(n) (1 << (((n) - 1) * 2 + 20))
154 #define IMGU_GP_STRMON_STAT_ACCS_PORT_ACC(n) (1 << (((n) - 1) * 2))
157 #define IMGU_GP_STRMON_STAT_ACCS2SP1_MON_PORT_ACC(n) (1 << (((n) - 1) * 2))
160 #define IMGU_GP_STRMON_STAT_ACCS2SP2_MON_PORT_ACC(n) (1 << (((n) - 1) * 2))
212 #define IMGU_GDC_LUT_MASK ((1 << 12) - 1) /* Range -1024..+1024 */
353 /* n = 0..IPU3_CSS_PIPE_ID_NUM-1 */
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