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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Drockchip-i2s.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip I2S controller
10 The I2S bus (Inter-IC sound bus) is a serial link for digital
14 - Heiko Stuebner <heiko@sntech.de>
17 - $ref: dai-common.yaml#
22 - const: rockchip,rk3066-i2s
23 - items:
[all …]
H A Drockchip,rk3288-hdmi-analog.txt1 ROCKCHIP RK3288 with HDMI and analog audio
4 - compatible: "rockchip,rk3288-hdmi-analog"
5 - rockchip,model: The user-visible name of this sound complex
6 - rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's
8 - rockchip,audio-codec: The phandle of the analog audio codec.
9 - rockchip,routing: A list of the connections between audio components.
16 - rockchip,hp-en-gpios = The phandle of the GPIO that power up/down the
18 - rockchip,hp-det-gpios = The phandle of the GPIO that detects the headphone
20 - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt
25 compatible = "rockchip,rk3288-hdmi-analog";
[all …]
/openbmc/linux/sound/soc/rockchip/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 snd-soc-rockchip-i2s-objs := rockchip_i2s.o
4 snd-soc-rockchip-i2s-tdm-objs := rockchip_i2s_tdm.o
5 snd-soc-rockchip-pdm-objs := rockchip_pdm.o
6 snd-soc-rockchip-spdif-objs := rockchip_spdif.o
8 obj-$(CONFIG_SND_SOC_ROCKCHIP_I2S) += snd-soc-rockchip-i2s.o
9 obj-$(CONFIG_SND_SOC_ROCKCHIP_PDM) += snd-soc-rockchip-pdm.o
10 obj-$(CONFIG_SND_SOC_ROCKCHIP_SPDIF) += snd-soc-rockchip-spdif.o
11 obj-$(CONFIG_SND_SOC_ROCKCHIP_I2S_TDM) += snd-soc-rockchip-i2s-tdm.o
13 snd-soc-rockchip-max98090-objs := rockchip_max98090.o
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 tristate "Rockchip I2S Device Driver"
15 Say Y or M if you want to add support for I2S driver for
16 Rockchip I2S device. The device supports up to maximum of
20 tristate "Rockchip I2S/TDM Device Driver"
24 Say Y or M if you want to add support for the I2S/TDM driver for
25 Rockchip I2S/TDM devices, found in Rockchip SoCs. These devices
26 interface between the AHB bus and the I2S bus, and support up to a
69 tristate "ASoC support multiple codecs for Rockchip RK3288 boards"
78 RK3288 boards using an analog output and the built-in HDMI audio.
H A Drk3288_hdmi_analog.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip machine ASoC driver for RK3288 boards that have an HDMI and analog
22 #include <sound/soc-dapm.h>
26 #define DRV_NAME "rk3288-snd-hdmi-analog"
36 struct rk_drvdata *machine = snd_soc_card_get_drvdata(w->dapm->card); in rk_hp_power()
38 if (!gpio_is_valid(machine->gpio_hp_en)) in rk_hp_power()
41 gpio_set_value_cansleep(machine->gpio_hp_en, in rk_hp_power()
94 return -EINVAL; in rk_hw_params()
100 if (ret && ret != -ENOTSUPP) { in rk_hw_params()
101 dev_err(codec_dai->dev, "Can't set cpu clock %d\n", ret); in rk_hw_params()
[all …]
H A Drockchip_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
7 * Author: Jianqun <jay.xu@rock-chips.com>
25 #define DRV_NAME "rockchip-i2s"
49 * I2S controller hopes to start the tx and rx together,
63 static int i2s_pinctrl_select_bclk_on(struct rk_i2s_dev *i2s) in i2s_pinctrl_select_bclk_on() argument
67 if (!IS_ERR(i2s->pinctrl) && !IS_ERR_OR_NULL(i2s->bclk_on)) in i2s_pinctrl_select_bclk_on()
68 ret = pinctrl_select_state(i2s->pinctrl, i2s->bclk_on); in i2s_pinctrl_select_bclk_on()
71 dev_err(i2s->dev, "bclk enable failed %d\n", ret); in i2s_pinctrl_select_bclk_on()
76 static int i2s_pinctrl_select_bclk_off(struct rk_i2s_dev *i2s) in i2s_pinctrl_select_bclk_off() argument
[all …]
/openbmc/u-boot/arch/arm/mach-rockchip/
H A DKconfig11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
14 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
23 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
41 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
42 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
44 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
55 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-rock2-square.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "rk3288-rock2-som.dtsi"
9 compatible = "radxa,rock2-square", "rockchip,rk3288";
12 stdout-path = "serial2:115200n8";
15 adc-keys {
16 compatible = "adc-keys";
17 io-channels = <&saradc 1>;
18 io-channel-names = "buttons";
[all …]
H A Drk3036.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
9 #include <dt-bindings/power/rk3036-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
H A Drk3288-veyron-mickey.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include "rk3288-veyron.dtsi"
10 #include "rk3288-veyron-broadcom-bluetooth.dtsi"
14 compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7",
15 "google,veyron-mickey-rev6", "google,veyron-mickey-rev5",
16 "google,veyron-mickey-rev4", "google,veyron-mickey-rev3",
17 "google,veyron-mickey-rev2", "google,veyron-mickey-rev1",
18 "google,veyron-mickey-rev0", "google,veyron-mickey",
19 "google,veyron", "rockchip,rk3288";
[all …]
H A Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
[all …]
H A Drk322x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
9 #include <dt-bindings/power/rk3228-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
H A Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
18 arm-pmu {
[all …]
H A Drk3288-firefly-reload.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device tree file for Firefly Rockchip RK3288 Core board
7 /dts-v1/;
8 #include "rk3288-firefly-reload-core.dtsi"
11 model = "Firefly-RK3288-reload";
12 compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288";
14 adc-keys {
15 compatible = "adc-keys";
16 io-channels = <&saradc 1>;
17 io-channel-names = "buttons";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drockchip,rk3288-cru.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3288 Clock and Reset Unit (CRU)
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 The RK3288 clock controller generates and supplies clocks to various
19 different so another dt-compatible is available. Noticed that it is only
25 preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
[all …]
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-cru.txt1 * Rockchip RK3288 Clock and Reset Unit
3 The RK3288 clock controller generates and supplies clock to various
9 - compatible: should be "rockchip,rk3288-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
22 preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
30 clock-output-names:
31 - "xin24m" - crystal input - required,
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3288.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power-domain/rk3288.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/video/rk3288.h>
14 compatible = "rockchip,rk3288";
[all …]
H A Drk322x.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3228-cru.h>
11 #include <dt-bindings/thermal/thermal.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
17 interrupt-parent = <&gic>;
[all …]
H A Drk3288-veyron-jerry.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
9 #include "rk3288-veyron-chromebook.dtsi"
10 #include "cros-ec-sbs.dtsi"
14 compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
15 "google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
16 "google,veyron-jerry-rev3", "google,veyron-jerry",
17 "google,veyron", "rockchip,rk3288";
20 stdout-path = &uart2;
23 panel_regulator: panel-regulator {
[all …]
H A Drk3328.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
33 #address-cells = <2>;
[all …]
H A Drk3188.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
18 enable-method = "rockchip,rk3066-smp";
22 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
25 operating-points = <
[all …]
H A Drk3288-veyron-mickey.dts6 * This file is dual-licensed: you can use it either under the terms
45 /dts-v1/;
46 #include "rk3288-veyron-chromebook.dtsi"
50 compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7",
51 "google,veyron-mickey-rev6", "google,veyron-mickey-rev5",
52 "google,veyron-mickey-rev4", "google,veyron-mickey-rev3",
53 "google,veyron-mickey-rev2", "google,veyron-mickey-rev1",
54 "google,veyron-mickey-rev0", "google,veyron-mickey",
55 "google,veyron", "rockchip,rk3288";
57 vcc_5v: vcc-5v {
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3368.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3368-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
[all …]
H A Drk3308.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/rk3308-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
[all …]
/openbmc/u-boot/drivers/sound/
H A Drockchip_i2s.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Taken from dc i2s/rockchip.c
12 #include <i2s.h>
51 struct rk_i2s_regs *regs = (struct rk_i2s_regs *)priv->base_address; in rockchip_i2s_init()
52 u32 bps = priv->bitspersample; in rockchip_i2s_init()
53 u32 lrf = priv->rfs; in rockchip_i2s_init()
54 u32 chn = priv->channels; in rockchip_i2s_init()
57 clrbits_le32(&regs->xfer, I2S_TX_TRAN_BIT); in rockchip_i2s_init()
58 mode = readl(&regs->txcr) & ~0x1f; in rockchip_i2s_init()
59 switch (priv->bitspersample) { in rockchip_i2s_init()
[all …]

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