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/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsa8775p-ride.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include "sa8775p-ride.dtsi"
12 compatible = "qcom,sa8775p-ride", "qcom,sa8775p";
16 phy-mode = "sgmii";
20 phy-mode = "sgmii";
24 compatible = "snps,dwmac-mdio";
25 #address-cells = <1>;
26 #size-cells = <0>;
29 compatible = "ethernet-phy-id0141.0dd4";
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp151a-prtt1c.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
8 #include "stm32mp151a-prtt1l.dtsi"
14 clock_ksz9031: clock-ksz9031 {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <25000000>;
20 clock_sja1105: clock-sja1105 {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
[all …]
H A Dstm32mp151a-prtt1a.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
8 #include "stm32mp151a-prtt1l.dtsi"
16 phy-handle = <&phy0>;
21 phy0: ethernet-phy@0 {
22 compatible = "ethernet-phy-id2000.0181";
24 interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>;
25 reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
26 reset-assert-us = <10>;
27 reset-deassert-us = <35>;
[all …]
H A Dstm32mp151a-prtt1s.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
8 #include "stm32mp151a-prtt1l.dtsi"
16 phy-handle = <&phy0>;
20 pinctrl-names = "default", "sleep";
21 pinctrl-0 = <&i2c1_pins_a>;
22 pinctrl-1 = <&i2c1_sleep_pins_a>;
23 clock-frequency = <100000>;
24 /delete-property/dmas;
25 /delete-property/dma-names;
[all …]
H A Dstm32mp157c-odyssey.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
8 #include "stm32mp157c-odyssey-som.dtsi"
11 model = "Seeed Studio Odyssey-STM32MP157C Board";
12 compatible = "seeed,stm32mp157c-odyssey",
13 "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
21 stdout-path = "serial0:115200n8";
26 pinctrl-names = "default", "sleep";
27 pinctrl-0 = <&dcmi_pins_b>;
28 pinctrl-1 = <&dcmi_sleep_pins_b>;
[all …]
/openbmc/linux/drivers/reset/
H A Dreset-imx7.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * i.MX7 System Reset Controller (SRC) driver
14 #include <linux/reset-controller.h>
16 #include <dt-bindings/reset/imx7-reset.h>
17 #include <dt-bindings/reset/imx8mq-reset.h>
18 #include <dt-bindings/reset/imx8mp-reset.h>
51 const struct imx7_src_signal *signal = &imx7src->signals[id]; in imx7_reset_update()
53 return regmap_update_bits(imx7src->regmap, in imx7_reset_update()
54 signal->offset, signal->bit, value); in imx7_reset_update()
92 unsigned long id, bool assert) in imx7_reset_set() argument
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qp-prtwd3.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
16 stdout-path = &uart4;
29 clock_ksz8081: clock-ksz8081 {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <50000000>;
35 clock_ksz9031: clock-ksz9031 {
36 compatible = "fixed-clock";
[all …]
H A Dimx6qdl-vicut1-12inch.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 gpio-keys {
8 compatible = "gpio-keys";
9 pinctrl-names = "default";
10 pinctrl-0 = <&pinctrl_gpiokeys>;
13 power-button {
17 wakeup-source;
24 power-supply = <&reg_3v3>;
28 remote-endpoint = <&lvds0_out>;
35 pinctrl-names = "default";
[all …]
H A Dimx6ull-dhcom-picoitx.dts1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
6 * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-SD-RTC-ADC-I-01D2
7 * DHCOR PCB number: 578-200 or newer
8 * DHCOM PCB number: 579-200 or newer
9 * PicoITX PCB number: 487-600 or newer
11 /dts-v1/;
13 #include "imx6ull-dhcom-som.dtsi"
14 #include "imx6ull-dhcom-som-cfg-sdcard.dtsi"
18 compatible = "dh,imx6ull-dhcom-picoitx", "dh,imx6ull-dhcom-som",
19 "dh,imx6ull-dhcor-som", "fsl,imx6ull";
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Dreset.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/reset-controller.h>
12 #include "reset.h"
18 rcdev->ops->assert(rcdev, id); in qcom_reset()
19 fsleep(rst->reset_map[id].udelay ?: 1); /* use 1 us as default */ in qcom_reset()
21 rcdev->ops->deassert(rcdev, id); in qcom_reset()
26 unsigned long id, bool assert) in qcom_reset_set_assert() argument
33 map = &rst->reset_map[id]; in qcom_reset_set_assert()
34 mask = map->bitmask ? map->bitmask : BIT(map->bit); in qcom_reset_set_assert()
36 regmap_update_bits(rst->regmap, map->reg, mask, assert ? mask : 0); in qcom_reset_set_assert()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
24 "#address-cells":
27 "#size-cells":
30 reset-gpios:
[all …]
H A Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_gen5.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
21 writel(val, &clock_manager_base->bypass); in cm_write_bypass()
28 writel(val, &clock_manager_base->ctrl); in cm_write_ctrl()
52 * Put all plls VCO registers back to reset value (bandgap power down).
53 * Put peripheral and main pll src to reset value to avoid glitch.
54 * Delay 5 us.
56 * Start 7 us timer.
58 * Wait for 7 us timer.
62 * Assert/deassert outreset all.
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3328-nanopi-r2c.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
9 /dts-v1/;
10 #include "rk3328-nanopi-r2s.dts"
14 compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
18 phy-handle = <&yt8521s>;
23 /delete-node/ ethernet-phy@1;
25 yt8521s: ethernet-phy@3 {
26 compatible = "ethernet-phy-ieee802.3-c22";
29 motorcomm,clk-out-frequency-hz = <125000000>;
[all …]
H A Drk3328-orangepi-r1-plus-lts.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
9 /dts-v1/;
10 #include "rk3328-orangepi-r1-plus.dts"
14 compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
18 /delete-property/ tx_delay;
19 /delete-property/ rx_delay;
21 phy-handle = <&yt8531c>;
22 phy-mode = "rgmii-id";
25 /delete-node/ ethernet-phy@1;
[all …]
/openbmc/qemu/hw/core/
H A Dresettable.c10 * See the COPYING file in the top-level directory.
29 * True if we are currently in reset enter phase.
34 * Note: These flags are only used to guarantee (using asserts) that the reset
36 * iothread mutex to ensure only one reset operation is in a progress at a
52 assert(!enter_phase_in_progress); in resettable_assert_reset()
66 assert(!enter_phase_in_progress); in resettable_release_reset()
70 exit_phase_in_progress -= 1; in resettable_release_reset()
78 ResettableState *s = rc->get_state(obj); in resettable_is_in_reset()
80 return s->count > 0; in resettable_is_in_reset()
91 if (rc->child_foreach) { in resettable_child_foreach()
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-debix-som-a-bmb-08.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "imx8mp-debix-som-a.dtsi"
12 model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08";
13 compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a",
22 stdout-path = &uart2;
25 reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 {
26 compatible = "regulator-fixed";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
[all …]
H A Dimx8dxl-evk.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
12 compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
22 stdout-path = &lpuart0;
30 reserved-memory {
31 #address-cells = <2>;
32 #size-cells = <2>;
37 * This will be automatically added to dtb if OP-TEE is installed.
40 * no-map;
46 compatible = "shared-dma-pool";
[all …]
/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxm-q200.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
11 #include "meson-gxm.dtsi"
12 #include "meson-gx-p23x-q20x.dtsi"
15 compatible = "amlogic,q200", "amlogic,s912", "amlogic,meson-gxm";
18 adc-keys {
19 compatible = "adc-keys";
20 io-channels = <&saradc 0>;
21 io-channel-names = "buttons";
[all …]
H A Dmeson-gxm-gt1-ultimate.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxm.dtsi"
9 #include "meson-gx-p23x-q20x.dtsi"
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
14 compatible = "azw,gt1-ultimate", "amlogic,s912", "amlogic,meson-gxm";
18 compatible = "gpio-leds";
20 led-white {
24 default-state = "on";
[all …]
H A Dmeson-gxl-s905d-p230.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
11 #include "meson-gxl-s905d.dtsi"
12 #include "meson-gx-p23x-q20x.dtsi"
15 compatible = "amlogic,p230", "amlogic,s905d", "amlogic,meson-gxl";
18 adc-keys {
19 compatible = "adc-keys";
20 io-channels = <&saradc 0>;
21 io-channel-names = "buttons";
[all …]
H A Dmeson-gxm-mecool-kiii-pro.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "meson-gxm.dtsi"
10 #include "meson-gx-p23x-q20x.dtsi"
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
15 compatible = "videostrong,gxm-kiii-pro", "amlogic,s912", "amlogic,meson-gxm";
23 adc-keys {
24 compatible = "adc-keys";
25 io-channels = <&saradc 0>;
[all …]
H A Dmeson-gxbb-p200.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb-p20x.dtsi"
11 #include <dt-bindings/input/input.h>
14 compatible = "amlogic,p200", "amlogic,meson-gxbb";
17 avdd18_usb_adc: regulator-avdd18_usb_adc {
18 compatible = "regulator-fixed";
19 regulator-name = "AVDD18_USB_ADC";
20 regulator-min-microvolt = <1800000>;
21 regulator-max-microvolt = <1800000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/thermal/
H A Dnvidia,tegra124-soctherm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/nvidia,tegra124-soctherm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 polled or interrupt-based thermal monitoring, CPU and GPU throttling based
21 - nvidia,tegra124-soctherm
22 - nvidia,tegra132-soctherm
23 - nvidia,tegra210-soctherm
[all …]
/openbmc/u-boot/doc/
H A DREADME.i2c4 While I2C supports multi-master buses this is difficult to get right.
6 Clock-stretching and the arbitrary time that an I2C transaction can take
8 When one or more masters can be reset independently part-way through a
11 U-Boot provides a scheme based on two 'claim' GPIOs, one driven by the
18 Since U-Boot runs on the AP, the terminology used is 'our' claim GPIO,
23 i2c-arb-gpio-challenge for the implementation.
28 - AP_CLAIM: output from AP, signalling to the EC that the AP wants the bus
29 - EC_CLAIM: output from EC, signalling to the AP that the EC wants the bus
31 The basic algorithm is to assert your line when you want the bus, then make
50 To release the bus, just de-assert the claim line.
[all …]

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