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/openbmc/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-samsung.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC PWM timers
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 Samsung SoCs contain PWM timer blocks which can be used for system clock source
15 and clock event timers, as well as to drive SoC outputs with PWM signal. Each
16 PWM timer block provides 5 PWM channels (not all of them can drive physical
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H A Dpwm-rockchip.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-rockchip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip PWM controller
10 - Heiko Stuebner <heiko@sntech.de>
15 - const: rockchip,rk2928-pwm
16 - const: rockchip,rk3288-pwm
17 - const: rockchip,rk3328-pwm
18 - const: rockchip,vop-pwm
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H A Dimx-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX PWM controller
10 - Philipp Zabel <p.zabel@pengutronix.de>
13 - $ref: pwm.yaml#
16 "#pwm-cells":
18 Should be 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.yaml
21 - 2
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H A Dpwm-fsl-ftm.txt1 Freescale FlexTimer Module (FTM) PWM controller
3 The same FTM PWM device can have a different endianness on different SoCs. The
6 for the endianness of the FTM PWM block as integrated into the existing SoCs:
8 SoC | FTM-PWM endianness
9 --------+-------------------
19 - compatible : should be "fsl,<soc>-ftm-pwm" and one of the following
21 - "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610
22 - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM
23 - reg: Physical base address and length of the controller's registers
24 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
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H A Dallwinner,sun4i-a10-pwm.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/allwinner,sun4i-a10-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 PWM
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#pwm-cells":
19 - const: allwinner,sun4i-a10-pwm
20 - const: allwinner,sun5i-a10s-pwm
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H A Dimg-pwm.txt1 *Imagination Technologies PWM DAC driver
4 - compatible: Should be "img,pistachio-pwm"
5 - reg: Should contain physical base address and length of pwm registers.
6 - clocks: Must contain an entry for each entry in clock-names.
7 See ../clock/clock-bindings.txt for details.
8 - clock-names: Must include the following entries.
9 - pwm: PWM operating clock.
10 - sys: PWM system interface clock.
11 - #pwm-cells: Should be 2. See pwm.yaml in this directory for the
13 - img,cr-periph: Must contain a phandle to the peripheral control
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H A Dpwm-sprd.txt1 Spreadtrum PWM controller
3 Spreadtrum SoCs PWM controller provides 4 PWM channels.
6 - compatible : Should be "sprd,ums512-pwm".
7 - reg: Physical base address and length of the controller's registers.
8 - clocks: The phandle and specifier referencing the controller's clocks.
9 - clock-names: Should contain following entries:
10 "pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3).
11 "enablen": for PWM channel n enable clock (n range: 0 ~ 3).
12 - #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
16 - assigned-clocks: Reference to the PWM clock entries.
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H A Dmediatek,pwm-disp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jitao Shi <jitao.shi@mediatek.com>
11 - Xinlei Lee <xinlei.lee@mediatek.com>
14 - $ref: pwm.yaml#
19 - enum:
20 - mediatek,mt2701-disp-pwm
21 - mediatek,mt6595-disp-pwm
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H A Dlpc1850-sct-pwm.txt1 * NXP LPC18xx State Configurable Timer - Pulse Width Modulator driver
4 - compatible: Should be "nxp,lpc1850-sct-pwm"
5 - reg: Should contain physical base address and length of pwm registers.
6 - clocks: Must contain an entry for each entry in clock-names.
7 See ../clock/clock-bindings.txt for details.
8 - clock-names: Must include the following entries.
9 - pwm: PWM operating clock.
10 - #pwm-cells: Should be 3. See pwm.yaml in this directory for the description
14 pwm: pwm@40000000 {
15 compatible = "nxp,lpc1850-sct-pwm";
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H A Dmediatek,mt2712-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/mediatek,mt2712-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek PWM Controller
10 - John Crispin <john@phrozen.org>
13 - $ref: pwm.yaml#
18 - enum:
19 - mediatek,mt2712-pwm
20 - mediatek,mt6795-pwm
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H A Dpwm-st.txt1 STMicroelectronics PWM driver bindings
2 --------------------------------------
5 - compatible : "st,pwm"
6 - #pwm-cells : Number of cells used to specify a PWM. First cell
7 specifies the per-chip index of the PWM to use and the
8 second cell is the period in nanoseconds - fixed to 2
10 - reg : Physical base address and length of the controller's
12 - pinctrl-names: Set to "default".
13 - pinctrl-0: List of phandles pointing to pin configuration nodes
14 for PWM module.
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H A Dsnps,dw-apb-timers-pwm2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/snps,dw-apb-timers-pwm2.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Synopsys DW-APB timers PWM controller
11 - Ben Dooks <ben.dooks@sifive.com>
14 This describes the DesignWare APB timers module when used in the PWM
24 - $ref: pwm.yaml#
28 const: snps,dw-apb-timers-pwm2
33 "#pwm-cells":
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dnvidia,tegra124-dfll.txt3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 the fast CPU cluster. It consists of a free-running voltage controlled
10 communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
13 - compatible : should be one of:
14 - "nvidia,tegra124-dfll": for Tegra124
15 - "nvidia,tegra210-dfll": for Tegra210
16 - reg : Defines the following set of registers, in the order listed:
17 - registers for the DFLL control logic.
18 - registers for the I2C output logic.
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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dingenic,tcu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 Documentation/arch/mips/ingenic-tcu.rst.
14 - Paul Cercueil <paul@crapouillou.net>
21 - ingenic,jz4740-tcu
22 - ingenic,jz4725b-tcu
23 - ingenic,jz4760-tcu
24 - ingenic,jz4760b-tcu
25 - ingenic,jz4770-tcu
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/openbmc/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa27x.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "dt-bindings/clock/pxa-clock.h"
11 pdma: dma-controller@40000000 {
12 compatible = "marvell,pdma-1.0";
15 #dma-cells = <2>;
17 #dma-channels = <32>;
18 dma-channels = <32>;
19 #dma-requests = <75>;
20 dma-requests = <75>;
24 pxairq: interrupt-controller@40d00000 {
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/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32f746.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "../armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
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H A Dstm32f429.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "../armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
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/openbmc/linux/drivers/clk/
H A Dclk-pwm.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * PWM (mis)used as clock output
7 #include <linux/clk-provider.h>
12 #include <linux/pwm.h>
16 struct pwm_device *pwm; member
29 return pwm_enable(clk_pwm->pwm); in clk_pwm_prepare()
36 pwm_disable(clk_pwm->pwm); in clk_pwm_unprepare()
44 return clk_pwm->fixed_rate; in clk_pwm_recalc_rate()
52 pwm_get_state(clk_pwm->pwm, &state); in clk_pwm_get_duty_cycle()
54 duty->num = state.duty_cycle; in clk_pwm_get_duty_cycle()
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/openbmc/qemu/include/hw/misc/
H A Dnpcm7xx_pwm.h2 * Nuvoton NPCM7xx PWM Module
19 #include "hw/clock.h"
23 /* Each PWM module holds 4 PWM channels. */
27 * Number of registers in one pwm module. Don't change this without increasing
34 * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty
35 * value of 100,000 the duty cycle for that PWM is 10%.
42 * struct NPCM7xxPWM - The state of a single PWM channel.
43 * @module: The PWM module that contains this channel.
45 * @running: Whether this PWM channel is generating output.
46 * @inverted: Whether this PWM channel is inverted.
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/openbmc/linux/drivers/pwm/
H A Dpwm-tegra.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
15 * The PWM clock frequency is divided by 256 before subdividing it based
17 * frequency for PWM output. The maximum output frequency that can be
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H A Dpwm-omap-dmtimer.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Also based on pwm-samsung.c
13 * PWM driver / controller, using the OMAP's dual-mode timers
15 * reloaded with the load value and the pwm output goes up.
20 * - When PWM is stopped, timer counter gets stopped immediately. This
21 * doesn't allow the current PWM period to complete and stops abruptly.
22 * - When PWM is running and changing both duty cycle and period,
25 * is updated while the pwm pin is high, current pwm period/duty_cycle
27 * - period for current cycle = current_period + new period
28 * - duty_cycle for current period = current period + new duty_cycle.
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H A Dpwm-sun4i.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 * - When outputing the source clock directly, the PWM logic will be bypassed
21 #include <linux/pwm.h>
47 #define PWM_PRD(prd) (((prd) - 1) << 16)
101 return readl(chip->base + offset); in sun4i_pwm_readl()
107 writel(val, chip->base + offset); in sun4i_pwm_writel()
111 struct pwm_device *pwm, in sun4i_pwm_get_state() argument
119 clk_rate = clk_get_rate(sun4i_pwm->clk); in sun4i_pwm_get_state()
121 return -EINVAL; in sun4i_pwm_get_state()
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/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drv1108.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 interrupt-parent = <&gic>;
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/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7779.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H1 (R8A77790) SoC
9 #include <dt-bindings/clock/r8a7779-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a7779-sysc.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
21 #address-cells = <1>;
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/openbmc/u-boot/arch/arm/dts/
H A Dstm32mp157c.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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