xref: /openbmc/linux/Documentation/devicetree/bindings/pwm/pwm-sprd.txt (revision c95baf12f5077419db01313ab61c2aac007d40cd)

Spreadtrum PWM controller

Spreadtrum SoCs PWM controller provides 4 PWM channels.

Required properties:
- compatible : Should be "sprd,ums512-pwm".
- reg: Physical base address and length of the controller's registers.
- clocks: The phandle and specifier referencing the controller's clocks.
- clock-names: Should contain following entries:
  "pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3).
  "enablen": for PWM channel n enable clock (n range: 0 ~ 3).
- #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
  the cells format.

Optional properties:
- assigned-clocks: Reference to the PWM clock entries.
- assigned-clock-parents: The phandle of the parent clock of PWM clock.

Example:
	pwms: pwm@32260000 {
		compatible = "sprd,ums512-pwm";
		reg = <0 0x32260000 0 0x10000>;
		clock-names = "pwm0", "enable0",
			"pwm1", "enable1",
			"pwm2", "enable2",
			"pwm3", "enable3";
		clocks = <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>,
		       <&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>,
		       <&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>,
		       <&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>;
		assigned-clocks = <&aon_clk CLK_PWM0>,
			<&aon_clk CLK_PWM1>,
			<&aon_clk CLK_PWM2>,
			<&aon_clk CLK_PWM3>;
		assigned-clock-parents = <&ext_26m>,
			<&ext_26m>,
			<&ext_26m>,
			<&ext_26m>;
		#pwm-cells = <2>;
	};