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/openbmc/qemu/target/arm/
H A Dptw.c33 * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
40 * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
49 * space used for ptw reads is the same as that of the security
52 * the ptw read are Secure and NonSecure, and the in_ptw_idx
76 static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw,
82 static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw,
167 * Return where we should do ptw loads from for a stage 2 walk.
533 * The security space for ptw reads is almost always the same in S2_security_space()
536 * the ptw read might be to the Secure or the NonSecure space in S2_security_space()
548 /* ptw loads are from phys: the mmu idx itself says which space */ in S2_security_space()
[all …]
H A Dmeson.build26 'ptw.c',
/openbmc/linux/arch/sh/include/cpu-sh4/cpu/
H A Dsh7724.h97 /* PTW */
134 /* ATAPI (PTA/PTB/PTK/PTR/PTS/PTW) */
249 /* SDHI1 (PTW) */
253 /* MMC (PTW/PTX)*/
H A Dsh7757.h94 /* PTW */
232 /* PTW (mobule: LBSC, EVC, SCIF) */
H A Dsh7722.h89 /* PTW */
H A Dsh7723.h95 /* PTW */
/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu.yaml283 the smmu ptw
308 - description: bus clock required for the smmu ptw
325 the smmu ptw
352 - description: bus clock required for the smmu ptw
372 the smmu ptw
426 the smmu ptw
/openbmc/linux/tools/perf/scripts/python/bin/
H A Dintel-pt-events-record8 echo "Options must include the Intel PT event e.g. -e intel_pt/pwr_evt,ptw/"
/openbmc/openbmc/meta-security/recipes-security/aircrack-ng/
H A Daircrack-ng_1.6.bb2 …MS attack along with some optimizations like KoreK attacks, as well as the PTW attack, thus making…
/openbmc/qemu/include/hw/arm/
H A Dsmmu-common.h193 * smmu_translate - Look for a translation in TLB, if not, do a PTW.
194 * Returns NULL on PTW error or incase of TLB permission errors.
/openbmc/linux/arch/csky/include/asm/
H A Dbarrier.h80 * Using three sync.is to prevent speculative PTW
/openbmc/linux/drivers/usb/chipidea/
H A Dbits.h77 /* PTS and PTW for non lpm version only */
/openbmc/linux/arch/loongarch/kernel/
H A Dproc.c83 if (cpu_has_ptw) seq_printf(m, " ptw"); in show_cpuinfo()
/openbmc/linux/arch/sh/boards/
H A Dboard-sh7757lcr.c446 /* SCIF3/4 (PTJ, PTW) */ in sh7757lcr_devices_setup()
529 /* EVC (PTV, PTW) */ in sh7757lcr_devices_setup()
/openbmc/linux/drivers/pinctrl/renesas/
H A Dpfc-sh7757.c461 /* PTW (mobule: LBSC, EVC, SCIF) */
691 /* PTW GPIO */
1012 /* PTW FN */
1290 /* PTW */
1623 /* PTW (mobule: LBSC, EVC, SCIF) */
H A Dpfc-sh7724.c483 /*PTW*/
712 /* PTW GPIO */
1075 /* PTW FN */
1332 /* PTW */
H A Dpfc-sh7723.c520 /* PTW GPIO */
862 /* PTW FN */
1093 /* PTW */
H A Dpfc-sh7722.c428 /* PTW */
919 /* PTW */
/openbmc/qemu/hw/arm/
H A Dsmmuv3.c271 s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTF, 2); /* AArch64 PTW only */ in smmuv3_init_regs()
365 /* Same PTW faults are reported but with CLASS = CD. */ in smmu_get_cd()
789 * Same PTW faults are reported but with CLASS = TT. in decode_cd()
950 /* All faults from PTW has S2 field. */ in smmuv3_do_translate()
/openbmc/qemu/target/i386/tcg/sysemu/
H A Dexcp_helper.c114 /* Does x86 really perform a rmw cycle on mmio for ptw? */ in ptw_setl_slow()
/openbmc/linux/arch/arm64/include/asm/
H A Dkvm_arm.h93 * PTW: Take a stage2 fault if a stage1 walk steps in device memory
/openbmc/qemu/target/mips/tcg/sysemu/
H A Dtlb_helper.c701 int ptw = (env->CP0_PWSize >> CP0PS_PTW) & 0x3F; in page_table_walk_refill() local
731 int ptindex = (address >> pf_ptw) & ((1 << ptw) - 1); in page_table_walk_refill()
/openbmc/linux/drivers/iommu/
H A Dexynos-iommu.c213 "PTW",
221 "PTW",
/openbmc/linux/arch/x86/events/intel/
H A Dpt.c113 PMU_FORMAT_ATTR(ptw, "config:12" );
375 /* FUPonPTW without PTW doesn't make sense */ in pt_event_valid()
/openbmc/linux/arch/arm/mm/
H A Dproc-v7.S84 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW

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