| /openbmc/linux/arch/mips/pic32/pic32mzda/ |
| H A D | early_clk.c | 31 u32 pllclk; in pic32_get_sysclk() local
54 pllclk = plliclk ? FRC_CLK : PIC32_POSC_FREQ; in pic32_get_sysclk()
72 osc_freq = ((pllclk / pllidiv) * pllmult) / pllodiv; in pic32_get_sysclk()
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | starfive,jh7110-syscrg.yaml | 109 <&pllclk 0>, <&pllclk 1>, <&pllclk 2>;
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| /openbmc/linux/drivers/clk/starfive/ |
| H A D | clk-starfive-jh7110-sys.c | 419 struct clk *pllclk; in jh7110_syscrg_probe() local
434 pllclk = clk_get(priv->dev, "pll0_out"); in jh7110_syscrg_probe()
435 if (IS_ERR(pllclk)) { in jh7110_syscrg_probe()
443 ret = clk_notifier_register(pllclk, &priv->pll_clk_nb); in jh7110_syscrg_probe()
449 pllclk = clk_get(priv->dev, "pll1_out"); in jh7110_syscrg_probe()
450 if (IS_ERR(pllclk)) { in jh7110_syscrg_probe()
457 clk_put(pllclk); in jh7110_syscrg_probe()
461 pllclk = clk_get(priv->dev, "pll2_out"); in jh7110_syscrg_probe()
462 if (IS_ERR(pllclk)) { in jh7110_syscrg_probe()
469 clk_put(pllclk); in jh7110_syscrg_probe()
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-xgene.c | 60 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); in xgene_clk_pll_is_enabled() local
63 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_is_enabled()
73 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); in xgene_clk_pll_recalc_rate() local
81 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_recalc_rate()
83 if (pllclk->version <= 1) { in xgene_clk_pll_recalc_rate()
84 if (pllclk->type == PLL_TYPE_PCP) { in xgene_clk_pll_recalc_rate()
113 pllclk->version); in xgene_clk_pll_recalc_rate()
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| /openbmc/linux/Documentation/devicetree/bindings/display/bridge/ |
| H A D | renesas,dsi.yaml | 62 - const: pllclk
156 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | microchip,clock.h | 12 #define PLLCLK 1 macro
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | microchip,pic32-clock.h | 17 #define PLLCLK 6 macro
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| /openbmc/u-boot/arch/mips/mach-pic32/ |
| H A D | cpu.c | 153 CLK_MHZ(rate(PLLCLK))); in soc_clk_dump()
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| /openbmc/linux/arch/riscv/boot/dts/starfive/ |
| H A D | jh7110.dtsi | 778 <&pllclk JH7110_PLLCLK_PLL0_OUT>,
779 <&pllclk JH7110_PLLCLK_PLL1_OUT>,
780 <&pllclk JH7110_PLLCLK_PLL2_OUT>;
795 pllclk: clock-controller { label
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| /openbmc/linux/drivers/clk/microchip/ |
| H A D | clk-pic32mzda.c | 208 clks[PLLCLK] = pic32_spll_clk_register(&sys_pll, core); in pic32mzda_clk_probe()
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| /openbmc/u-boot/drivers/clk/ |
| H A D | clk_pic32.c | 353 case PLLCLK: in pic32_get_rate()
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| /openbmc/qemu/include/hw/misc/ |
| H A D | stm32l4x5_rcc_internals.h | 354 "pllclk"
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| /openbmc/linux/arch/arm64/boot/dts/renesas/ |
| H A D | r9a07g054.dtsi | 794 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
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| H A D | r9a07g044.dtsi | 789 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
|