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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra234-xusb.yaml61 - const: pll_e
145 "pll_e";
H A Dnvidia,tegra194-xusb.yaml57 - const: pll_e
160 "pll_e";
H A Dnvidia,tegra186-xusb.yaml57 - const: pll_e
156 "pll_u_480m", "clk_m", "pll_e";
H A Dnvidia,tegra124-xusb.yaml71 - const: pll_e
183 "clk_m", "pll_e";
H A Dnvidia,tegra210-xusb.yaml63 - const: pll_e
167 "pll_u_480m", "clk_m", "pll_e";
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt59 - pll_e
194 clock-names = "pex", "afi", "pll_e";
299 clock-names = "pex", "afi", "pll_e", "cml";
403 clock-names = "pex", "afi", "pll_e", "cml";
499 clock-names = "pex", "afi", "pll_e", "cml";
597 clock-names = "afi", "pex", "pll_e";
/openbmc/linux/include/dt-bindings/clock/
H A Dsunplus,sp7021-clkc.h77 #define PLL_E 65 macro
/openbmc/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_lvds.c136 unsigned int pll_e; member
249 pll->pll_e = e; in rcar_lvds_d3_e3_pll_calc()
261 output = fin * pll->pll_n / pll->pll_m / (1 << pll->pll_e) in rcar_lvds_d3_e3_pll_calc()
269 pll->pll_m, pll->pll_n, pll->pll_e, pll->div); in rcar_lvds_d3_e3_pll_calc()
288 if (pll.pll_e > 0) in rcar_lvds_pll_setup_d3_e3()
290 | LVDPLLCR_PLLE(pll.pll_e - 1); in rcar_lvds_pll_setup_d3_e3()
/openbmc/linux/drivers/clk/
H A Dclk-sp7021.c635 hws[PLL_E] = sp_pll_register(dev, "plle", &pd_ext, PLLE_CTL, in sp7021_clk_probe()
637 if (IS_ERR(hws[PLL_E])) in sp7021_clk_probe()
638 return PTR_ERR(hws[PLL_E]); in sp7021_clk_probe()
639 pd_e.hw = hws[PLL_E]; in sp7021_clk_probe()
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dnvidia,tegra20-car.txt149 118 pll_e
/openbmc/linux/drivers/usb/host/
H A Dxhci-tegra.c285 struct clk *pll_e; member
830 err = clk_prepare_enable(tegra->pll_e); in tegra_xusb_clk_enable()
873 clk_disable_unprepare(tegra->pll_e); in tegra_xusb_clk_enable()
879 clk_disable_unprepare(tegra->pll_e); in tegra_xusb_clk_disable()
1663 tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e"); in tegra_xusb_probe()
1664 if (IS_ERR(tegra->pll_e)) { in tegra_xusb_probe()
1665 err = PTR_ERR(tegra->pll_e); in tegra_xusb_probe()
1666 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err); in tegra_xusb_probe()
/openbmc/linux/drivers/pci/controller/
H A Dpci-tegra.c334 struct clk *pll_e; member
1160 clk_disable_unprepare(pcie->pll_e); in tegra_pcie_power_off()
1218 err = clk_prepare_enable(pcie->pll_e); in tegra_pcie_power_on()
1266 pcie->pll_e = devm_clk_get(dev, "pll_e"); in tegra_pcie_clocks_get()
1267 if (IS_ERR(pcie->pll_e)) in tegra_pcie_clocks_get()
1268 return PTR_ERR(pcie->pll_e); in tegra_pcie_clocks_get()
/openbmc/u-boot/arch/arm/dts/
H A Dtegra124.dtsi46 clock-names = "pex", "afi", "pll_e", "cml";
619 clock-names = "sata", "sata-oob", "cml1", "pll_e";
669 "pll_u_480m", "clk_m", "pll_e";
H A Dtegra20.dtsi611 clock-names = "pex", "afi", "pll_e";
H A Dtegra210.dtsi43 clock-names = "pex", "afi", "pll_e", "cml";
H A Dtegra30.dtsi43 clock-names = "pex", "afi", "pll_e", "cml";
/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra30.c556 { .con_id = "pll_e", .dt_id = TEGRA30_CLK_PLL_E },
1031 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra30_periph_clk_init()
1036 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra30_periph_clk_init()
1374 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base, in tegra30_car_probe()
H A Dclk-tegra124.c1058 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
1064 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
1203 clk = tegra_clk_register_plle_tegra114("pll_e", "pll_ref", in tegra124_pll_init()
1205 clk_register_clkdev(clk, "pll_e", NULL); in tegra124_pll_init()
H A Dclk-tegra20.c435 { .con_id = "pll_e", .dt_id = TEGRA20_CLK_PLL_E },
692 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, in tegra20_pll_init()
H A Dclk-tegra210.c3144 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init()
3150 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init()
3357 clk = tegra_clk_register_plle_tegra210("pll_e", "pll_ref", in tegra210_pll_init()
3359 clk_register_clkdev(clk, "pll_e", NULL); in tegra210_pll_init()
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi48 clock-names = "pex", "afi", "pll_e", "cml";
679 "pll_u_480m", "clk_m", "pll_e";
H A Dtegra210.dtsi47 clock-names = "pex", "afi", "pll_e", "cml";
1033 "pll_u_480m", "clk_m", "pll_e";
H A Dtegra186.dtsi1128 "pll_u_480m", "clk_m", "pll_e";
1369 clock-names = "pex", "afi", "pll_e";
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124.dtsi53 clock-names = "pex", "afi", "pll_e", "cml";
728 "pll_u_480m", "clk_m", "pll_e";
H A Dtegra20.dtsi808 clock-names = "pex", "afi", "pll_e";

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