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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_read_leveling.c1 // SPDX-License-Identifier: GPL-2.0
55 * Desc: Execute the Read leveling phase by HW
56 * Args: dram_info - main struct
57 * freq - current sequence frequency
65 /* Debug message - Start Read leveling procedure */ in ddr3_read_leveling_hw()
66 DEBUG_RL_S("DDR3 - Read Leveling - Starting HW RL procedure\n"); in ddr3_read_leveling_hw()
74 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
76 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_hw()
91 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
93 dram_info->rl_max_phase = 0; in ddr3_read_leveling_hw()
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H A Dddr3_write_leveling.c1 // SPDX-License-Identifier: GPL-2.0
58 * Desc: Execute Write leveling phase by HW
59 * Args: freq - current sequence frequency
60 * dram_info - main struct
66 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
70 /* Debug message - Start Read leveling procedure */ in ddr3_write_leveling_hw()
71 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw()
86 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
87 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
103 * Read results to arrays - Results are required for WL in ddr3_write_leveling_hw()
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H A Dddr3_pbs.c1 // SPDX-License-Identifier: GPL-2.0
44 /* PBS locked dq (per pup) */
70 * Desc: Execute the PBS TX phase.
92 /* bit array for unlock pups - used to repeat on the RX operation */ in ddr3_pbs_tx()
102 DEBUG_PBS_S("DDR3 - PBS TX - Starting PBS TX procedure\n"); in ddr3_pbs_tx()
104 pups = dram_info->num_of_total_pups; in ddr3_pbs_tx()
105 max_pup = dram_info->num_of_total_pups; in ddr3_pbs_tx()
110 /* [0] = 1 - Enable SW override */ in ddr3_pbs_tx()
111 /* 0x15B8 - Training SW 2 Register */ in ddr3_pbs_tx()
113 DEBUG_PBS_S("DDR3 - PBS RX - SW Override Enabled\n"); in ddr3_pbs_tx()
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/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-driver-zynqmp-fpga1 What: /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status
9 https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
18 BIT(2) 0: MMCMs/PLLs are not locked
19 1: MMCMs/PLLs are locked
24 BIT(4) 0: Start-up sequence has not finished
25 1: Start-up sequence has finished
27 BIT(5) 0: All I/Os are placed in High-Z state
30 BIT(6) 0: Flip-flops and block RAM are write disabled
31 1: Flip-flops and block RAM are write enabled
54 BIT(17) System Monitor over-temperature if set
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H A Dsysfs-bus-iio-frequency-ad95238 Contact: linux-iio@vger.kernel.org
18 Contact: linux-iio@vger.kernel.org
21 pllY is locked.
25 Contact: linux-iio@vger.kernel.org
29 with their predefined phase offsets (out_altvoltageY_phase).
/openbmc/linux/drivers/iio/frequency/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 # Phase-Locked Loop (PLL) frequency synthesizers
27 # Phase-Locked Loop (PLL) frequency synthesizers
30 menu "Phase-Locked Loop (PLL) frequency synthesizers"
90 Downconverter with integrated Fractional-N PLL and VCO.
/openbmc/linux/drivers/media/dvb-frontends/
H A Dtda8261.c1 // SPDX-License-Identifier: GPL-2.0-or-later
29 const struct tda8261_config *config = state->config; in tda8261_read()
31 struct i2c_msg msg = { .addr = config->addr, .flags = I2C_M_RD,.buf = buf, .len = 1 }; in tda8261_read()
33 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) in tda8261_read()
41 const struct tda8261_config *config = state->config; in tda8261_write()
43 struct i2c_msg msg = { .addr = config->addr, .flags = 0, .buf = buf, .len = 4 }; in tda8261_write()
45 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) in tda8261_write()
53 struct tda8261_state *state = fe->tuner_priv; in tda8261_get_status()
64 pr_debug("%s: Tuner Phase Locked\n", __func__); in tda8261_get_status()
76 struct tda8261_state *state = fe->tuner_priv; in tda8261_get_frequency()
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H A Dtda665x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
27 const struct tda665x_config *config = state->config; in tda665x_read()
29 struct i2c_msg msg = { .addr = config->addr, .flags = I2C_M_RD, .buf = buf, .len = 2 }; in tda665x_read()
31 err = i2c_transfer(state->i2c, &msg, 1); in tda665x_read()
43 const struct tda665x_config *config = state->config; in tda665x_write()
45 struct i2c_msg msg = { .addr = config->addr, .flags = 0, .buf = buf, .len = length }; in tda665x_write()
47 err = i2c_transfer(state->i2c, &msg, 1); in tda665x_write()
59 struct tda665x_state *state = fe->tuner_priv; in tda665x_get_frequency()
61 *frequency = state->frequency; in tda665x_get_frequency()
68 struct tda665x_state *state = fe->tuner_priv; in tda665x_get_status()
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H A Ddib3000mb_priv.h1 /* SPDX-License-Identifier: GPL-2.0-only */
17 { pr_err("while sending 0x%04x to 0x%04x.", val, reg); return -EREMOTEIO; }
159 * Dual Automatic-Gain-Control
160 * - gains RF in tuner (AGC1)
161 * - gains IF after filtering (AGC2)
173 /* phase noise */
255 /* phase noise compensation inhibition */
297 * data diversity when having more than one chip on-board
313 /* time frame for Bit-Error-Rate calculation */
320 /* 142 - 152 FIFO parameters
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/openbmc/linux/include/linux/
H A Dww_mutex.h1 /* SPDX-License-Identifier: GPL-2.0 */
35 #define ww_mutex_base_is_locked(b) rt_mutex_base_is_locked(&(b)->rtmutex)
88 * ww_mutex_init - initialize the w/w mutex
96 * It is not allowed to initialize an already locked mutex.
101 ww_mutex_base_init(&lock->base, ww_class->mutex_name, &ww_class->mutex_key); in ww_mutex_init()
102 lock->ctx = NULL; in ww_mutex_init()
104 lock->ww_class = ww_class; in ww_mutex_init()
109 * ww_acquire_init - initialize a w/w acquire context
115 * Context-based w/w mutex acquiring can be done in any order whatsoever within
119 * Mixing of context-based w/w mutex acquiring and single w/w mutex locking can
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/openbmc/linux/drivers/clk/qcom/
H A Dclk-alpha-pll.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/clk-provider.h>
12 #include "clk-regmap.h"
75 * struct clk_alpha_pll - phase locked loop (PLL)
97 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
100 * @width: width of post-divider
101 * @post_div_shift: shift to differentiate between odd & even post-divider
102 * @post_div_table: table with PLL odd and even post-divider settings
103 * @num_post_div: Number of PLL post-divider settings
H A Dclk-pll.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
13 * struct pll_freq_tbl - PLL frequency table
28 * struct clk_pll - phase locked loop (PLL)
37 * @hw: handle between common and hardware-specific interfaces
/openbmc/linux/Documentation/devicetree/bindings/clock/ti/
H A Dapll.txt3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped APLL with usually two selectable input clocks
7 (reference clock and bypass clock), with analog phase locked
10 modes (locked, low power stop etc.) APLL mostly behaves like
13 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
18 - #clock-cells : from common clock binding; shall be set to 0.
19 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
20 - reg : address and length of the register set for controlling the APLL.
22 "control" - contains the control register offset
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H A Ddpll.txt3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped DPLL with usually two selectable input clocks
7 (reference clock and bypass clock), with digital phase locked
10 modes (locked, low power stop etc.) This binding has several
11 sub-types, which effectively result in slightly different setup
14 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be one of:
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
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/openbmc/linux/arch/arm/mach-ep93xx/
H A Dhardware.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/arm/mach-ep93xx/include/mach/hardware.h
13 * required high-frequency clocks, the processor uses two phase-locked-
/openbmc/linux/sound/soc/tegra/
H A Dtegra20_spdif.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * tegra20_spdif.h - Definitions for Tegra20 SPDIF driver
6 * Copyright (C) 2011 - NVIDIA, Inc.
9 * Copyright (c) 2008-2009, NVIDIA Corporation
125 * This bit is asserted when the receiver first locked onto the
169 /* B-preamble detection status: 0=not detected, 1=B-preamble detected */
210 * bi-phase period.
215 /* Data strobe mode: 0=Auto-locked 1=Manual locked */
219 * Manual data strobe time within the bi-phase clock period (in terms of
220 * the number of over-sampling clocks).
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8qm-lvds-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
15 groups of four data lanes of LVDS data streams. A phase-locked
30 - fsl,imx8qm-lvds-phy
31 - mixel,28fdsoi-lvds-1250-8ch-tx-pll
33 "#phy-cells":
42 power-domains:
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/openbmc/linux/include/uapi/linux/
H A Dpps.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
5 * Copyright (C) 2005-2009 Rodolfo Giometti <giometti@linux.it>
43 /* 32-bit vs. 64-bit compatibility.
120 use a phase-locked loop */
122 use a frequency-locked loop */
124 * Here begins the implementation-specific part!
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1 // SPDX-License-Identifier: GPL-2.0
55 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) in ddr3_tip_dynamic_read_leveling()
59 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
60 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
77 * Phase 1: Load pattern (using ODPG) in ddr3_tip_dynamic_read_leveling()
81 * assuming non multi-CS configuration in ddr3_tip_dynamic_read_leveling()
103 * Phase 2: ODPG to Read Leveling mode in ddr3_tip_dynamic_read_leveling()
118 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
119 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
121 tm->interface_params[if_id].speed_bin_index; in ddr3_tip_dynamic_read_leveling()
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/openbmc/linux/Documentation/driver-api/nvdimm/
H A Dsecurity.rst6 ---------------
16 ------------------
22 that DIMM. The following states are available: disabled, unlocked, locked,
28 update <old_keyid> <new_keyid> - enable or update passphrase.
29 disable <keyid> - disable enabled security and remove key.
30 freeze - freeze changing of security states.
31 erase <keyid> - delete existing user encryption key.
32 overwrite <keyid> - wipe the entire nvdimm.
33 master_update <keyid> <new_keyid> - enable or update master passphrase.
34 master_erase <keyid> - delete existing user encryption key.
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/openbmc/linux/include/drm/
H A Dtask_barrier.h27 * Reusable 2 PHASE task barrier (rendez-vous point) implementation for N tasks.
28 * Based on the Little book of semaphores - https://greenteapress.com/wp/semaphores/
57 tb->n = 0; in task_barrier_init()
58 atomic_set(&tb->count, 0); in task_barrier_init()
59 sema_init(&tb->enter_turnstile, 0); in task_barrier_init()
60 sema_init(&tb->exit_turnstile, 0); in task_barrier_init()
65 tb->n++; in task_barrier_add_task()
70 tb->n--; in task_barrier_rem_task()
76 * When all thread passed this code the entry barrier is back to locked state.
80 if (atomic_inc_return(&tb->count) == tb->n) in task_barrier_enter()
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/openbmc/linux/Documentation/filesystems/
H A Dxfs-online-fsck-design.rst1 .. SPDX-License-Identifier: GPL-2.0
8 Heading 3 uses "----"
25 - To help kernel distributors understand exactly what the XFS online fsck
28 - To help people reading the code to familiarize themselves with the relevant
31 - To help developers maintaining the system by capturing the reasons
59 - Provide a hierarchy of names through which application programs can associate
62 - Virtualize physical storage media across those names, and
64 - Retrieve the named data blobs at any time.
66 - Examine resource usage.
79 cross-references different types of metadata records with each other to look
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/openbmc/linux/arch/sparc/include/asm/
H A Dspitfire.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define TSB_EXTENSION_P 0x0000000000000048 /* Ultra-III and later */
25 #define TSB_EXTENSION_S 0x0000000000000050 /* Ultra-III and later, D-TLB only */
26 #define TSB_EXTENSION_N 0x0000000000000058 /* Ultra-III and later */
27 #define TLB_TAG_ACCESS_EXT 0x0000000000000060 /* Ultra-III+ and later */
38 #define SPITFIRE_HIGHEST_LOCKED_TLBENT (64 - 1)
39 #define CHEETAH_HIGHEST_LOCKED_TLBENT (16 - 1)
58 * to identify the CPU type in the setup phase
201 /* Cheetah has "all non-locked" tlb flushes. */
218 /* Cheetah has a 4-tlb layout so direct access is a bit different.
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/openbmc/bmcweb/redfish-core/schema/dmtf/csdl/
H A DCircuit_v1.xml1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ -->
4 <!--# Redfish Schema: Circuit v1.8.1 -->
5 <!--# -->
6 <!--# For a detailed change log, see the README file contained in the DSP8010 bundle, -->
7 <!--# available at http://www.dmtf.org/standards/redfish -->
8 <!--# Copyright 2014-2024 DMTF. -->
9 <!--# For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright -->
10 <!--################################################################################ -->
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/openbmc/linux/drivers/scsi/aic7xxx/
H A Daic79xx.reg4 * Copyright (c) 1994-2001, 2004 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
19 * 3. Neither the names of the above-listed copyright holders nor the names
62 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
69 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
76 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \
136 BAD_PHASE, /* unknown scsi bus phase */
142 * Returned to data phase
187 * A command with a non-zero
839 * PCI-X Control
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