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/openbmc/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
24 reg-names:
[all …]
/openbmc/linux/drivers/soc/tegra/
H A Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
19 #include <linux/clk/tegra.h>
37 #include <linux/pinctrl/pinconf-generic.h>
56 #include <dt-bindings/interrupt-controller/arm-gic.h>
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
26 mpp2 2 gpo, nand(io4), spi(sck)
28 mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
31 mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
[all …]
H A Dmarvell,armada-98dx3236-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
8 - reg: register specifier of MPP registers
16 mpp2 2 gpo, spi0(sck), dev(ad10)
19 mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs)
20 mpp6 6 gpo, sd0(clk), dev(a2)
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dtegra20-trimslice.dts1 /dts-v1/;
10 stdout-path = &uarta;
25 clock-frequency = <216000000>;
30 spi-max-frequency = <25000000>;
33 pcie-controller@80003000 {
36 avdd-pex-supply = <&pci_vdd_reg>;
37 vdd-pex-supply = <&pci_vdd_reg>;
38 avdd-pex-pll-supply = <&pci_vdd_reg>;
39 avdd-plle-supply = <&pci_vdd_reg>;
40 vddio-pex-clk-supply = <&pci_clk_reg>;
[all …]
H A Dtegra30-apalis.dts1 /dts-v1/;
10 stdout-path = &uarta;
35 pcie-controller@00003000 {
37 avdd-pexa-supply = <&vdd2_reg>;
38 vdd-pexa-supply = <&vdd2_reg>;
39 avdd-pexb-supply = <&vdd2_reg>;
40 vdd-pexb-supply = <&vdd2_reg>;
41 avdd-pex-pll-supply = <&vdd2_reg>;
42 avdd-plle-supply = <&ldo6_reg>;
43 vddio-pex-ctl-supply = <&sys_3v3_reg>;
[all …]
H A Dtegra186.dtsi2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/power/tegra186-powergate.h>
7 #include <dt-bindings/reset/tegra186-reset.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 compatible = "nvidia,tegra186-gpio";
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H A Dtegra20.dtsi1 #include <dt-bindings/clock/tegra20-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 interrupt-parent = <&lic>;
13 compatible = "nvidia,tegra20-host1x", "simple-bus";
19 reset-names = "host1x";
21 #address-cells = <1>;
22 #size-cells = <1>;
27 compatible = "nvidia,tegra20-mpe";
[all …]
H A Dtegra20-harmony.dts1 /dts-v1/;
3 #include <dt-bindings/input/input.h>
11 stdout-path = &uartd;
38 display-timings {
41 clock-frequency = <42430000>;
44 hback-porch = <138>;
45 hfront-porch = <34>;
46 hsync-len = <136>;
47 vback-porch = <21>;
48 vfront-porch = <4>;
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_lib.c1 // SPDX-License-Identifier: GPL-2.0
17 #define ENDED_OK "High speed PHY - Ended Successfully\n"
32 #define MV_BOARD_ETM_MODULE_ID 2
35 #define ETM_MODULE_DETECT 2
131 /* SERDES module (only PEX model is supported now) */ in board_modules_scan()
142 if ((reg_read(GPP_DATA_IN_REG(2)) & MV_GPP66) == 0x0) in board_modules_scan()
192 return &serdes_info_tbl[board_id - BOARD_ID_BASE][serdes_cfg_val]; in board_serdes_cfg_get()
213 return (info->line0_7 >> (line_num << 2)) & 0xF; in get_line_cfg()
215 return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF; in get_line_cfg()
234 * configuration pulse for the PEX link detection might lead to
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dhigh_speed_env_spec.c1 // SPDX-License-Identifier: GPL-2.0
24 * serdes_seq_db - holds all serdes sequences, their size and the
30 #define ENDED_OK "High speed PHY - Ended Successfully\n"
38 #define SERDES_ALREADY_IN_USE 2
46 /* 0 1 2 3 */
47 { 1, 1, 1, 1 }, /* PEX */
54 { 2, 0, 0, 0 } /* RXAUI */
63 /* Selector mapping for A380-A0 and A390-Z1 */
65 /* 0 1 2 3 4 5 6 */
89 /* Selector mapping for PEX by 4 confiuration */
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-apalis-v1.1.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 * 2GB: V1.1A, V1.1B
16 avdd-pexa-supply = <&vdd2_reg>;
17 avdd-pexb-supply = <&vdd2_reg>;
18 avdd-pex-pll-supply = <&vdd2_reg>;
19 avdd-plle-supply = <&ldo6_reg>;
20 hvdd-pex-supply = <&reg_module_3v3>;
21 vddio-pex-ctl-supply = <&reg_module_3v3>;
22 vdd-pexa-supply = <&vdd2_reg>;
23 vdd-pexb-supply = <&vdd2_reg>;
[all …]
H A Dtegra30-apalis.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C, V1.0E
15 avdd-pexa-supply = <&vdd2_reg>;
16 avdd-pexb-supply = <&vdd2_reg>;
17 avdd-pex-pll-supply = <&vdd2_reg>;
18 avdd-plle-supply = <&ldo6_reg>;
19 hvdd-pex-supply = <&reg_module_3v3>;
20 vddio-pex-ctl-supply = <&reg_module_3v3>;
21 vdd-pexa-supply = <&vdd2_reg>;
22 vdd-pexb-supply = <&vdd2_reg>;
[all …]
H A Dtegra124-apalis-v1.2.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2016-2018 Toradex AG
7 #include "tegra124-apalis-emc.dtsi"
11 * Compatible for Revisions 2GB: V1.2A
21 avddio-pex-supply = <&reg_1v05_vdd>;
22 avdd-pex-pll-supply = <&reg_1v05_vdd>;
23 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
24 dvddio-pex-supply = <&reg_1v05_vdd>;
25 hvdd-pex-pll-e-supply = <&reg_module_3v3>;
26 hvdd-pex-supply = <&reg_module_3v3>;
[all …]
H A Dtegra124-apalis.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
7 #include "tegra124-apalis-emc.dtsi"
11 * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A
20 avddio-pex-supply = <&reg_1v05_vdd>;
21 avdd-pex-pll-supply = <&reg_1v05_vdd>;
22 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
23 dvddio-pex-supply = <&reg_1v05_vdd>;
24 hvdd-pex-pll-e-supply = <&reg_module_3v3>;
25 hvdd-pex-supply = <&reg_module_3v3>;
[all …]
H A Dtegra20-trimslice.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
6 #include "tegra20-cpu-opp.dtsi"
19 stdout-path = "serial0:115200n8";
30 vdd-supply = <&hdmi_vdd_reg>;
31 pll-supply = <&hdmi_pll_reg>;
33 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
34 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
40 pinctrl-names = "default";
[all …]
H A Dtegra20-tamonten.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 stdout-path = "serial0:115200n8";
24 vdd-supply = <&hdmi_vdd_reg>;
25 pll-supply = <&hdmi_pll_reg>;
27 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
28 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
34 pinctrl-names = "default";
35 pinctrl-0 = <&state_default>;
252 state_i2cmux_ddc: pinmux-i2cmux-ddc {
263 state_i2cmux_idle: pinmux-i2cmux-idle {
[all …]
/openbmc/linux/drivers/pci/controller/
H A Dpci-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
16 #include <linux/clk.h>
98 #define AFI_INTR_INI_DECODE_ERROR 2
117 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
127 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
155 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
245 #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16)
256 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
[all …]
/openbmc/u-boot/board/freescale/mpc837xerdb/
H A Dpci.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
65 volatile sysconf83xx_t *sysconf = &immr->sysconf; in pci_init_board()
66 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; in pci_init_board() local
67 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; in pci_init_board()
68 volatile law83xx_t *pcie_law = sysconf->pcielaw; in pci_init_board()
71 u32 spridr = in_be32(&immr->sysconf.spridr); in pci_init_board()
74 clk->occr |= 0xf8000000; in pci_init_board()
86 /* There is no PEX in MPC8379 parts. */ in pci_init_board()
91 clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, in pci_init_board()
[all …]
/openbmc/u-boot/board/freescale/mpc837xemds/
H A Dpci.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
79 volatile sysconf83xx_t *sysconf = &immr->sysconf; in pci_init_board()
80 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; in pci_init_board() local
81 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; in pci_init_board()
82 volatile law83xx_t *pcie_law = sysconf->pcielaw; in pci_init_board()
85 u32 spridr = in_be32(&immr->sysconf.spridr); in pci_init_board()
92 clk->occr |= 0xf8000000; in pci_init_board()
106 /* There is no PEX in MPC8379 parts. */ in pci_init_board()
118 clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, in pci_init_board()
[all …]
/openbmc/u-boot/board/freescale/bsc9132qds/
H A DREADME2 --------
4 Microcell, Picocell, and Enterprise-Femto base station market subsegments.
7 core technologies with MAPLE-B2P baseband acceleration processing elements
15 - Power Architecture subsystem including two e500 processors with
16 512-Kbyte shared L2 cache
17 - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
19 - 32 Kbyte of shared M3 memory
20 - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
21 Processing (MAPLE-B2P)
22 - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
[all …]
/openbmc/u-boot/drivers/pci/
H A Dpci_tegra.c1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (c) 2008-2009, NVIDIA Corporation.
9 * Copyright (c) 2013-2014, NVIDIA Corporation.
12 #define pr_fmt(fmt) "tegra-pcie: " fmt
15 #include <clk.h>
21 #include <power-domain.h>
33 #include <asm/arch-tegra/xusb-padctl.h>
34 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
41 * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
88 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
[all …]
/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra20.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include <linux/clk/tegra.h>
15 #include <dt-bindings/clock/tegra20-car.h>
17 #include "clk.h"
18 #include "clk-id.h"
26 #define OSC_CTRL_OSC_FREQ_12MHZ (2u<<30)
33 #define OSC_CTRL_PLL_REF_DIV_4 (2u<<28)
86 #define CCLK_RUN_POLICY 2
138 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
[all …]

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