| /openbmc/linux/drivers/staging/vc04_services/vchiq-mmal/ |
| H A D | mmal-msg-format.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
19 #include "mmal-msg-common.h"
27 u32 bits_per_sample; /* Bits per sample */
39 * FourCC specifying the color space of the video stream. See the
40 * MmalColorSpace "pre-defined color spaces" for some examples.
56 /* Definition of an elementary stream format (MMAL_ES_FORMAT_T) */
61 * stream.
65 * stream.
70 * elementary stream
73 u32 bitrate; /* Bitrate in bits per second */
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
13 …Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed th…
26 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
42 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
46 … uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
51 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
55 … uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
64 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
73 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
78 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
13 …Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed th…
26 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
42 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
46 … uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
51 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
55 … uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
64 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
73 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
78 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/broadwell/ |
| H A D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
13 …Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed th…
26 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
42 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
46 … uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
51 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
55 … uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
64 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
73 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
78 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/jaketown/ |
| H A D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
17 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
20 …Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes…
25 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce…
32 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre…
61 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
69 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
93 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.…
101 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
141 …-end in delivering uops. Microcode assists are used for complex instructions or scenarios that ca…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/sandybridge/ |
| H A D | frontend.json | 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
17 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
20 …Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes…
25 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce…
32 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre…
61 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
69 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
93 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.…
101 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.…
141 …-end in delivering uops. Microcode assists are used for complex instructions or scenarios that ca…
[all …]
|
| /openbmc/linux/Documentation/userspace-api/media/v4l/ |
| H A D | pixfmt-compressed.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
8 .. _compressed-formats:
18 .. flat-table:: Compressed Image Formats
19 :header-rows: 1
20 :stub-columns: 0
23 * - Identifier
24 - Code
25 - Details
26 * .. _V4L2-PIX-FMT-JPEG:
28 - ``V4L2_PIX_FMT_JPEG``
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/haswellx/ |
| H A D | frontend.json | 6 "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
25 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
32 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
56 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
83 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.…
91 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
136 … event counts cycles during which the microcode sequencer assisted the Front-end in delivering uop…
141 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered …
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/haswell/ |
| H A D | frontend.json | 6 "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
25 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
32 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
56 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
83 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.…
91 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
136 … event counts cycles during which the microcode sequencer assisted the Front-end in delivering uop…
141 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered …
[all …]
|
| /openbmc/linux/drivers/staging/media/atomisp/pci/ |
| H A D | ia_css_stream_public.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
36 IA_CSS_INPUT_MODE_FIFO, /** data from input-fifo */
37 IA_CSS_INPUT_MODE_TPG, /** data from test-pattern generator */
38 IA_CSS_INPUT_MODE_PRBS, /** data from pseudo-random bit stream */
51 stream */
66 enum atomisp_input_format format; /** Format of input stream. This data
69 int linked_isys_stream_id; /** default value is -1, other value means
81 enum atomisp_input_format format; /** Format of input stream. This data
87 /* Input stream description. This describes how input will flow into the
114 unsigned int pixels_per_clock; /** Number of pixels per clock, which can be
[all …]
|
| /openbmc/linux/sound/usb/line6/ |
| H A D | pcm.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2010 Markus Grabner (grabner@icg.tugraz.at)
20 number of USB frames per URB
21 The Line 6 Windows driver always transmits two frames per packet, but
23 with only one frame per packet.
37 #define get_substream(line6pcm, stream) \ argument
38 (line6pcm->pcm->streams[stream].substream)
49 capture and playback stream, which must be shared between these
54 or capture stream. Both can contain the bit flag corresponding to
60 the running flag indicates whether the stream is running.
[all …]
|
| /openbmc/linux/sound/firewire/dice/ |
| H A D | dice-interface.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 * block read transactions with at least quadlet-aligned offset and length.
12 * Writes are not allowed except where noted; quadlet-sized registers must be
15 * All values are in big endian. The DICE firmware runs on a little-endian CPU
16 * and just byte-swaps _all_ quadlets on the bus, so values without endianness
17 * (e.g. strings) get scrambled and must be byte-swapped again by the driver.
32 * size values are measured in quadlets. Read-only.
50 * Stores the full 64-bit address (node ID and offset in the node's address
60 * A bitmask with asynchronous events; read-only. When any event(s) happen,
74 /* Other bits may be used for device-specific events. */
[all …]
|
| /openbmc/libcper/sections/ |
| H A D | cper-section-ccix-per.c | 2 * Describes functions for converting CCIX PER log CPER sections from binary and JSON format
12 #include <libcper/cper-utils.h>
13 #include <libcper/sections/cper-section-ccix-per.h>
15 //Converts a single CCIX PER log CPER section into JSON IR.
23 json_object_new_uint64(ccix_error->Length)); in cper_section_ccix_per_to_ir()
27 ccix_error->ValidBits, 3, CCIX_PER_ERROR_VALID_BITFIELD_NAMES); in cper_section_ccix_per_to_ir()
32 json_object_new_int(ccix_error->CcixSourceId)); in cper_section_ccix_per_to_ir()
34 json_object_new_int(ccix_error->CcixPortId)); in cper_section_ccix_per_to_ir()
36 //CCIX PER Log. in cper_section_ccix_per_to_ir()
40 ccix_error->Length - sizeof(EFI_CCIX_PER_LOG_DATA); in cper_section_ccix_per_to_ir()
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/media/ |
| H A D | cdns,csi2tx.txt | 1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10 - reg: base address and size of the memory mapped region
11 - clocks: phandles to the clocks driving the controller
12 - clock-names: must contain:
15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
20 - phy-names: must contain "dphy"
[all …]
|
| /openbmc/linux/include/linux/ |
| H A D | slimbus.h | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011-2017, The Linux Foundation
16 * struct slim_eaddr - Enumeration address for a SLIMbus device
30 * enum slim_device_status - slim device status
44 * struct slim_device - Slim device handle.
49 * @laddr: 1-byte Logical address of this device.
52 * @stream_list_lock: lock to protect the stream list
56 * Pointer to this structure is used by client-driver as a handle.
72 * struct slim_driver - SLIMbus 'generic device' (slave) device driver
78 * - The device reports present and gets a laddr assigned
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| H A D | frontend.json | 6 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
22 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec…
27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
30 …Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed th…
41 …unts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-…
52 …d a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means st…
88 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
94 …er an interval where the front-end delivered no uops for a period of at least 1 cycle which was no…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/skylake/ |
| H A D | frontend.json | 6 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
22 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec…
27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
30 …Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed th…
41 …unts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-…
52 …d a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means st…
88 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
94 …er an interval where the front-end delivered no uops for a period of at least 1 cycle which was no…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/skylakex/ |
| H A D | frontend.json | 6 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
22 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec…
27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
30 …Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed th…
41 …unts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-…
52 …d a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means st…
88 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
94 …er an interval where the front-end delivered no uops for a period of at least 1 cycle which was no…
[all …]
|
| /openbmc/linux/drivers/media/pci/cx18/ |
| H A D | cx18-driver.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Derived from ivtv-driver.h
24 #include <linux/i2c-algo-bit.h>
33 #include <media/v4l2-common.h>
34 #include <media/v4l2-ioctl.h>
35 #include <media/v4l2-device.h>
36 #include <media/v4l2-fh.h>
38 #include <media/i2c/ir-kbd-i2c.h>
39 #include "cx18-mailbox.h"
40 #include "cx18-av-core.h"
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_validation.c | 41 uint32_t pxl_clk = timing->pix_clk_100hz; in get_tmds_output_pixel_clock_100hz()
43 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) in get_tmds_output_pixel_clock_100hz()
45 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) in get_tmds_output_pixel_clock_100hz()
48 if (timing->display_color_depth == COLOR_DEPTH_101010) in get_tmds_output_pixel_clock_100hz()
50 else if (timing->display_color_depth == COLOR_DEPTH_121212) in get_tmds_output_pixel_clock_100hz()
60 const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps; in dp_active_dongle_validate_timing()
62 switch (dpcd_caps->dongle_type) { in dp_active_dongle_validate_timing()
66 if (timing->pixel_encoding == PIXEL_ENCODING_RGB) in dp_active_dongle_validate_timing()
74 if (dpcd_caps->dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER && in dp_active_dongle_validate_timing()
75 dongle_caps->extendedCapValid == true) { in dp_active_dongle_validate_timing()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/ |
| H A D | TODO | 5 1. Base this on drm-next - WIP
11 3. WIP - Drop page flip helper and use DRM's version
14 4. DONE - Flatten all DC objects
15 * dc_stream/core_stream/stream should just be dc_stream
28 5. DONE - Rename DC objects to align more with DRM
29 * dc_surface -> dc_plane_state
30 * dc_stream -> dc_stream_state
33 6. DONE - Per-plane and per-stream validation
36 7. WIP - Per-plane and per-stream commit
39 8. WIP - Split pipe_ctx into plane and stream resource structs
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/ivytown/ |
| H A D | frontend.json | 6 "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
27 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre…
43 …"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB…
46 …"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTL…
59 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
68 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
95 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
99 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/ivybridge/ |
| H A D | frontend.json | 6 "PublicDescription": "Number of front end re-steers due to BPU misprediction.",
11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
27 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre…
43 …"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB…
46 …"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTL…
59 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
68 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
95 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
99 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.…
[all …]
|
| /openbmc/linux/include/linux/soundwire/ |
| H A D | sdw_amd.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
21 * is invoked. If set, a complete bus reset and re-enumeration will
22 * be performed when the bus restarts. In-band wake interrupts are
44 * @name: SoundWire stream name
45 * @stream: stream runtime
47 * @stream_type: Stream type
51 struct sdw_stream_runtime *stream; member
57 * struct amd_sdw_manager - amd manager driver context
62 * @reg_mask: register mask structure per manager instance
74 * @wake_en_mask: wake enable mask per SoundWire manager
|
| /openbmc/linux/sound/virtio/ |
| H A D | virtio_chmap.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * virtio-snd: Virtio sound device
10 /* VirtIO->ALSA channel position map */
52 * virtsnd_chmap_parse_cfg() - Parse the channel map configuration.
58 * Return: 0 on success, -errno on failure.
62 struct virtio_device *vdev = snd->vdev; in virtsnd_chmap_parse_cfg()
66 virtio_cread_le(vdev, struct virtio_snd_config, chmaps, &snd->nchmaps); in virtsnd_chmap_parse_cfg()
67 if (!snd->nchmaps) in virtsnd_chmap_parse_cfg()
70 snd->chmaps = devm_kcalloc(&vdev->dev, snd->nchmaps, in virtsnd_chmap_parse_cfg()
71 sizeof(*snd->chmaps), GFP_KERNEL); in virtsnd_chmap_parse_cfg()
[all …]
|