1c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
2b285192aSMauro Carvalho Chehab /*
3b285192aSMauro Carvalho Chehab * cx18 driver internal defines and structures
4b285192aSMauro Carvalho Chehab *
5b285192aSMauro Carvalho Chehab * Derived from ivtv-driver.h
6b285192aSMauro Carvalho Chehab *
7b285192aSMauro Carvalho Chehab * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
8b285192aSMauro Carvalho Chehab * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net>
9b285192aSMauro Carvalho Chehab */
10b285192aSMauro Carvalho Chehab
11b285192aSMauro Carvalho Chehab #ifndef CX18_DRIVER_H
12b285192aSMauro Carvalho Chehab #define CX18_DRIVER_H
13b285192aSMauro Carvalho Chehab
14b285192aSMauro Carvalho Chehab #include <linux/module.h>
15b285192aSMauro Carvalho Chehab #include <linux/moduleparam.h>
16b285192aSMauro Carvalho Chehab #include <linux/init.h>
17b285192aSMauro Carvalho Chehab #include <linux/delay.h>
18174cd4b1SIngo Molnar #include <linux/sched/signal.h>
19b285192aSMauro Carvalho Chehab #include <linux/fs.h>
20b285192aSMauro Carvalho Chehab #include <linux/pci.h>
21b285192aSMauro Carvalho Chehab #include <linux/interrupt.h>
22b285192aSMauro Carvalho Chehab #include <linux/spinlock.h>
23b285192aSMauro Carvalho Chehab #include <linux/i2c.h>
24b285192aSMauro Carvalho Chehab #include <linux/i2c-algo-bit.h>
25b285192aSMauro Carvalho Chehab #include <linux/list.h>
26b285192aSMauro Carvalho Chehab #include <linux/unistd.h>
27b285192aSMauro Carvalho Chehab #include <linux/pagemap.h>
28b285192aSMauro Carvalho Chehab #include <linux/workqueue.h>
29b285192aSMauro Carvalho Chehab #include <linux/mutex.h>
30b285192aSMauro Carvalho Chehab #include <linux/slab.h>
31b285192aSMauro Carvalho Chehab #include <asm/byteorder.h>
32b285192aSMauro Carvalho Chehab
33b285192aSMauro Carvalho Chehab #include <media/v4l2-common.h>
34b285192aSMauro Carvalho Chehab #include <media/v4l2-ioctl.h>
35b285192aSMauro Carvalho Chehab #include <media/v4l2-device.h>
36b285192aSMauro Carvalho Chehab #include <media/v4l2-fh.h>
37b285192aSMauro Carvalho Chehab #include <media/tuner.h>
38b5dcee22SMauro Carvalho Chehab #include <media/i2c/ir-kbd-i2c.h>
39b285192aSMauro Carvalho Chehab #include "cx18-mailbox.h"
40b285192aSMauro Carvalho Chehab #include "cx18-av-core.h"
41b285192aSMauro Carvalho Chehab #include "cx23418.h"
42b285192aSMauro Carvalho Chehab
43b285192aSMauro Carvalho Chehab /* DVB */
44fada1935SMauro Carvalho Chehab #include <media/demux.h>
45fada1935SMauro Carvalho Chehab #include <media/dmxdev.h>
46fada1935SMauro Carvalho Chehab #include <media/dvb_demux.h>
47fada1935SMauro Carvalho Chehab #include <media/dvb_frontend.h>
48fada1935SMauro Carvalho Chehab #include <media/dvb_net.h>
49fada1935SMauro Carvalho Chehab #include <media/dvbdev.h>
50b285192aSMauro Carvalho Chehab
51*643e8350SHans Verkuil /* vb2 YUV support */
52*643e8350SHans Verkuil #include <media/videobuf2-vmalloc.h>
53b285192aSMauro Carvalho Chehab
54b285192aSMauro Carvalho Chehab #ifndef CONFIG_PCI
55b285192aSMauro Carvalho Chehab # error "This driver requires kernel PCI support."
56b285192aSMauro Carvalho Chehab #endif
57b285192aSMauro Carvalho Chehab
58b285192aSMauro Carvalho Chehab #define CX18_MEM_OFFSET 0x00000000
59b285192aSMauro Carvalho Chehab #define CX18_MEM_SIZE 0x04000000
60b285192aSMauro Carvalho Chehab #define CX18_REG_OFFSET 0x02000000
61b285192aSMauro Carvalho Chehab
62b285192aSMauro Carvalho Chehab /* Maximum cx18 driver instances. */
63b285192aSMauro Carvalho Chehab #define CX18_MAX_CARDS 32
64b285192aSMauro Carvalho Chehab
65b285192aSMauro Carvalho Chehab /* Supported cards */
66b285192aSMauro Carvalho Chehab #define CX18_CARD_HVR_1600_ESMT 0 /* Hauppauge HVR 1600 (ESMT memory) */
67b285192aSMauro Carvalho Chehab #define CX18_CARD_HVR_1600_SAMSUNG 1 /* Hauppauge HVR 1600 (Samsung memory) */
68b285192aSMauro Carvalho Chehab #define CX18_CARD_COMPRO_H900 2 /* Compro VideoMate H900 */
69b285192aSMauro Carvalho Chehab #define CX18_CARD_YUAN_MPC718 3 /* Yuan MPC718 */
70b285192aSMauro Carvalho Chehab #define CX18_CARD_CNXT_RAPTOR_PAL 4 /* Conexant Raptor PAL */
71b285192aSMauro Carvalho Chehab #define CX18_CARD_TOSHIBA_QOSMIO_DVBT 5 /* Toshiba Qosmio Interal DVB-T/Analog*/
72b285192aSMauro Carvalho Chehab #define CX18_CARD_LEADTEK_PVR2100 6 /* Leadtek WinFast PVR2100 */
73b285192aSMauro Carvalho Chehab #define CX18_CARD_LEADTEK_DVR3100H 7 /* Leadtek WinFast DVR3100 H */
74b285192aSMauro Carvalho Chehab #define CX18_CARD_GOTVIEW_PCI_DVD3 8 /* GoTView PCI DVD3 Hybrid */
75b285192aSMauro Carvalho Chehab #define CX18_CARD_HVR_1600_S5H1411 9 /* Hauppauge HVR 1600 s5h1411/tda18271*/
76b285192aSMauro Carvalho Chehab #define CX18_CARD_LAST 9
77b285192aSMauro Carvalho Chehab
78b285192aSMauro Carvalho Chehab #define CX18_ENC_STREAM_TYPE_MPG 0
79b285192aSMauro Carvalho Chehab #define CX18_ENC_STREAM_TYPE_TS 1
80b285192aSMauro Carvalho Chehab #define CX18_ENC_STREAM_TYPE_YUV 2
81b285192aSMauro Carvalho Chehab #define CX18_ENC_STREAM_TYPE_VBI 3
82b285192aSMauro Carvalho Chehab #define CX18_ENC_STREAM_TYPE_PCM 4
83b285192aSMauro Carvalho Chehab #define CX18_ENC_STREAM_TYPE_IDX 5
84b285192aSMauro Carvalho Chehab #define CX18_ENC_STREAM_TYPE_RAD 6
85b285192aSMauro Carvalho Chehab #define CX18_MAX_STREAMS 7
86b285192aSMauro Carvalho Chehab
87b285192aSMauro Carvalho Chehab /* system vendor and device IDs */
88b285192aSMauro Carvalho Chehab #define PCI_VENDOR_ID_CX 0x14f1
89b285192aSMauro Carvalho Chehab #define PCI_DEVICE_ID_CX23418 0x5b7a
90b285192aSMauro Carvalho Chehab
91b285192aSMauro Carvalho Chehab /* subsystem vendor ID */
92b285192aSMauro Carvalho Chehab #define CX18_PCI_ID_HAUPPAUGE 0x0070
93b285192aSMauro Carvalho Chehab #define CX18_PCI_ID_COMPRO 0x185b
94b285192aSMauro Carvalho Chehab #define CX18_PCI_ID_YUAN 0x12ab
95b285192aSMauro Carvalho Chehab #define CX18_PCI_ID_CONEXANT 0x14f1
96b285192aSMauro Carvalho Chehab #define CX18_PCI_ID_TOSHIBA 0x1179
97b285192aSMauro Carvalho Chehab #define CX18_PCI_ID_LEADTEK 0x107D
98b285192aSMauro Carvalho Chehab #define CX18_PCI_ID_GOTVIEW 0x5854
99b285192aSMauro Carvalho Chehab
100b285192aSMauro Carvalho Chehab /* ======================================================================== */
101b285192aSMauro Carvalho Chehab /* ========================== START USER SETTABLE DMA VARIABLES =========== */
102b285192aSMauro Carvalho Chehab /* ======================================================================== */
103b285192aSMauro Carvalho Chehab
104b285192aSMauro Carvalho Chehab /* DMA Buffers, Default size in MB allocated */
105b285192aSMauro Carvalho Chehab #define CX18_DEFAULT_ENC_TS_BUFFERS 1
106b285192aSMauro Carvalho Chehab #define CX18_DEFAULT_ENC_MPG_BUFFERS 2
107b285192aSMauro Carvalho Chehab #define CX18_DEFAULT_ENC_IDX_BUFFERS 1
108b285192aSMauro Carvalho Chehab #define CX18_DEFAULT_ENC_YUV_BUFFERS 2
109b285192aSMauro Carvalho Chehab #define CX18_DEFAULT_ENC_VBI_BUFFERS 1
110b285192aSMauro Carvalho Chehab #define CX18_DEFAULT_ENC_PCM_BUFFERS 1
111b285192aSMauro Carvalho Chehab
112b285192aSMauro Carvalho Chehab /* Maximum firmware DMA buffers per stream */
113b285192aSMauro Carvalho Chehab #define CX18_MAX_FW_MDLS_PER_STREAM 63
114b285192aSMauro Carvalho Chehab
115b285192aSMauro Carvalho Chehab /* YUV buffer sizes in bytes to ensure integer # of frames per buffer */
116b285192aSMauro Carvalho Chehab #define CX18_UNIT_ENC_YUV_BUFSIZE (720 * 32 * 3 / 2) /* bytes */
117b285192aSMauro Carvalho Chehab #define CX18_625_LINE_ENC_YUV_BUFSIZE (CX18_UNIT_ENC_YUV_BUFSIZE * 576/32)
118b285192aSMauro Carvalho Chehab #define CX18_525_LINE_ENC_YUV_BUFSIZE (CX18_UNIT_ENC_YUV_BUFSIZE * 480/32)
119b285192aSMauro Carvalho Chehab
120b285192aSMauro Carvalho Chehab /* IDX buffer size should be a multiple of the index entry size from the chip */
121b285192aSMauro Carvalho Chehab struct cx18_enc_idx_entry {
122b285192aSMauro Carvalho Chehab __le32 length;
123b285192aSMauro Carvalho Chehab __le32 offset_low;
124b285192aSMauro Carvalho Chehab __le32 offset_high;
125b285192aSMauro Carvalho Chehab __le32 flags;
126b285192aSMauro Carvalho Chehab __le32 pts_low;
127b285192aSMauro Carvalho Chehab __le32 pts_high;
128b285192aSMauro Carvalho Chehab } __attribute__ ((packed));
129b285192aSMauro Carvalho Chehab #define CX18_UNIT_ENC_IDX_BUFSIZE \
130b285192aSMauro Carvalho Chehab (sizeof(struct cx18_enc_idx_entry) * V4L2_ENC_IDX_ENTRIES)
131b285192aSMauro Carvalho Chehab
132b285192aSMauro Carvalho Chehab /* DMA buffer, default size in kB allocated */
133b285192aSMauro Carvalho Chehab #define CX18_DEFAULT_ENC_TS_BUFSIZE 32
134b285192aSMauro Carvalho Chehab #define CX18_DEFAULT_ENC_MPG_BUFSIZE 32
135b285192aSMauro Carvalho Chehab #define CX18_DEFAULT_ENC_IDX_BUFSIZE (CX18_UNIT_ENC_IDX_BUFSIZE * 1 / 1024 + 1)
136b285192aSMauro Carvalho Chehab #define CX18_DEFAULT_ENC_YUV_BUFSIZE (CX18_UNIT_ENC_YUV_BUFSIZE * 3 / 1024 + 1)
137b285192aSMauro Carvalho Chehab #define CX18_DEFAULT_ENC_PCM_BUFSIZE 4
138b285192aSMauro Carvalho Chehab
139b285192aSMauro Carvalho Chehab /* i2c stuff */
140b285192aSMauro Carvalho Chehab #define I2C_CLIENTS_MAX 16
141b285192aSMauro Carvalho Chehab
142b285192aSMauro Carvalho Chehab /* debugging */
143b285192aSMauro Carvalho Chehab
144b285192aSMauro Carvalho Chehab /* Flag to turn on high volume debugging */
145b285192aSMauro Carvalho Chehab #define CX18_DBGFLG_WARN (1 << 0)
146b285192aSMauro Carvalho Chehab #define CX18_DBGFLG_INFO (1 << 1)
147b285192aSMauro Carvalho Chehab #define CX18_DBGFLG_API (1 << 2)
148b285192aSMauro Carvalho Chehab #define CX18_DBGFLG_DMA (1 << 3)
149b285192aSMauro Carvalho Chehab #define CX18_DBGFLG_IOCTL (1 << 4)
150b285192aSMauro Carvalho Chehab #define CX18_DBGFLG_FILE (1 << 5)
151b285192aSMauro Carvalho Chehab #define CX18_DBGFLG_I2C (1 << 6)
152b285192aSMauro Carvalho Chehab #define CX18_DBGFLG_IRQ (1 << 7)
153b285192aSMauro Carvalho Chehab /* Flag to turn on high volume debugging */
154b285192aSMauro Carvalho Chehab #define CX18_DBGFLG_HIGHVOL (1 << 8)
155b285192aSMauro Carvalho Chehab
156b285192aSMauro Carvalho Chehab /* NOTE: extra space before comma in 'fmt , ## args' is required for
157b285192aSMauro Carvalho Chehab gcc-2.95, otherwise it won't compile. */
158b285192aSMauro Carvalho Chehab #define CX18_DEBUG(x, type, fmt, args...) \
159b285192aSMauro Carvalho Chehab do { \
160b285192aSMauro Carvalho Chehab if ((x) & cx18_debug) \
161b285192aSMauro Carvalho Chehab v4l2_info(&cx->v4l2_dev, " " type ": " fmt , ## args); \
162b285192aSMauro Carvalho Chehab } while (0)
163b285192aSMauro Carvalho Chehab #define CX18_DEBUG_WARN(fmt, args...) CX18_DEBUG(CX18_DBGFLG_WARN, "warning", fmt , ## args)
164b285192aSMauro Carvalho Chehab #define CX18_DEBUG_INFO(fmt, args...) CX18_DEBUG(CX18_DBGFLG_INFO, "info", fmt , ## args)
165b285192aSMauro Carvalho Chehab #define CX18_DEBUG_API(fmt, args...) CX18_DEBUG(CX18_DBGFLG_API, "api", fmt , ## args)
166b285192aSMauro Carvalho Chehab #define CX18_DEBUG_DMA(fmt, args...) CX18_DEBUG(CX18_DBGFLG_DMA, "dma", fmt , ## args)
167b285192aSMauro Carvalho Chehab #define CX18_DEBUG_IOCTL(fmt, args...) CX18_DEBUG(CX18_DBGFLG_IOCTL, "ioctl", fmt , ## args)
168b285192aSMauro Carvalho Chehab #define CX18_DEBUG_FILE(fmt, args...) CX18_DEBUG(CX18_DBGFLG_FILE, "file", fmt , ## args)
169b285192aSMauro Carvalho Chehab #define CX18_DEBUG_I2C(fmt, args...) CX18_DEBUG(CX18_DBGFLG_I2C, "i2c", fmt , ## args)
170b285192aSMauro Carvalho Chehab #define CX18_DEBUG_IRQ(fmt, args...) CX18_DEBUG(CX18_DBGFLG_IRQ, "irq", fmt , ## args)
171b285192aSMauro Carvalho Chehab
172b285192aSMauro Carvalho Chehab #define CX18_DEBUG_HIGH_VOL(x, type, fmt, args...) \
173b285192aSMauro Carvalho Chehab do { \
174b285192aSMauro Carvalho Chehab if (((x) & cx18_debug) && (cx18_debug & CX18_DBGFLG_HIGHVOL)) \
175b285192aSMauro Carvalho Chehab v4l2_info(&cx->v4l2_dev, " " type ": " fmt , ## args); \
176b285192aSMauro Carvalho Chehab } while (0)
177b285192aSMauro Carvalho Chehab #define CX18_DEBUG_HI_WARN(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_WARN, "warning", fmt , ## args)
178b285192aSMauro Carvalho Chehab #define CX18_DEBUG_HI_INFO(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_INFO, "info", fmt , ## args)
179b285192aSMauro Carvalho Chehab #define CX18_DEBUG_HI_API(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_API, "api", fmt , ## args)
180b285192aSMauro Carvalho Chehab #define CX18_DEBUG_HI_DMA(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_DMA, "dma", fmt , ## args)
181b285192aSMauro Carvalho Chehab #define CX18_DEBUG_HI_IOCTL(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_IOCTL, "ioctl", fmt , ## args)
182b285192aSMauro Carvalho Chehab #define CX18_DEBUG_HI_FILE(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_FILE, "file", fmt , ## args)
183b285192aSMauro Carvalho Chehab #define CX18_DEBUG_HI_I2C(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_I2C, "i2c", fmt , ## args)
184b285192aSMauro Carvalho Chehab #define CX18_DEBUG_HI_IRQ(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_IRQ, "irq", fmt , ## args)
185b285192aSMauro Carvalho Chehab
186b285192aSMauro Carvalho Chehab /* Standard kernel messages */
187b285192aSMauro Carvalho Chehab #define CX18_ERR(fmt, args...) v4l2_err(&cx->v4l2_dev, fmt , ## args)
188b285192aSMauro Carvalho Chehab #define CX18_WARN(fmt, args...) v4l2_warn(&cx->v4l2_dev, fmt , ## args)
189b285192aSMauro Carvalho Chehab #define CX18_INFO(fmt, args...) v4l2_info(&cx->v4l2_dev, fmt , ## args)
190b285192aSMauro Carvalho Chehab
191b285192aSMauro Carvalho Chehab /* Messages for internal subdevs to use */
192b285192aSMauro Carvalho Chehab #define CX18_DEBUG_DEV(x, dev, type, fmt, args...) \
193b285192aSMauro Carvalho Chehab do { \
194b285192aSMauro Carvalho Chehab if ((x) & cx18_debug) \
195b285192aSMauro Carvalho Chehab v4l2_info(dev, " " type ": " fmt , ## args); \
196b285192aSMauro Carvalho Chehab } while (0)
197b285192aSMauro Carvalho Chehab #define CX18_DEBUG_WARN_DEV(dev, fmt, args...) \
198b285192aSMauro Carvalho Chehab CX18_DEBUG_DEV(CX18_DBGFLG_WARN, dev, "warning", fmt , ## args)
199b285192aSMauro Carvalho Chehab #define CX18_DEBUG_INFO_DEV(dev, fmt, args...) \
200b285192aSMauro Carvalho Chehab CX18_DEBUG_DEV(CX18_DBGFLG_INFO, dev, "info", fmt , ## args)
201b285192aSMauro Carvalho Chehab #define CX18_DEBUG_API_DEV(dev, fmt, args...) \
202b285192aSMauro Carvalho Chehab CX18_DEBUG_DEV(CX18_DBGFLG_API, dev, "api", fmt , ## args)
203b285192aSMauro Carvalho Chehab #define CX18_DEBUG_DMA_DEV(dev, fmt, args...) \
204b285192aSMauro Carvalho Chehab CX18_DEBUG_DEV(CX18_DBGFLG_DMA, dev, "dma", fmt , ## args)
205b285192aSMauro Carvalho Chehab #define CX18_DEBUG_IOCTL_DEV(dev, fmt, args...) \
206b285192aSMauro Carvalho Chehab CX18_DEBUG_DEV(CX18_DBGFLG_IOCTL, dev, "ioctl", fmt , ## args)
207b285192aSMauro Carvalho Chehab #define CX18_DEBUG_FILE_DEV(dev, fmt, args...) \
208b285192aSMauro Carvalho Chehab CX18_DEBUG_DEV(CX18_DBGFLG_FILE, dev, "file", fmt , ## args)
209b285192aSMauro Carvalho Chehab #define CX18_DEBUG_I2C_DEV(dev, fmt, args...) \
210b285192aSMauro Carvalho Chehab CX18_DEBUG_DEV(CX18_DBGFLG_I2C, dev, "i2c", fmt , ## args)
211b285192aSMauro Carvalho Chehab #define CX18_DEBUG_IRQ_DEV(dev, fmt, args...) \
212b285192aSMauro Carvalho Chehab CX18_DEBUG_DEV(CX18_DBGFLG_IRQ, dev, "irq", fmt , ## args)
213b285192aSMauro Carvalho Chehab
214b285192aSMauro Carvalho Chehab #define CX18_DEBUG_HIGH_VOL_DEV(x, dev, type, fmt, args...) \
215b285192aSMauro Carvalho Chehab do { \
216b285192aSMauro Carvalho Chehab if (((x) & cx18_debug) && (cx18_debug & CX18_DBGFLG_HIGHVOL)) \
217b285192aSMauro Carvalho Chehab v4l2_info(dev, " " type ": " fmt , ## args); \
218b285192aSMauro Carvalho Chehab } while (0)
219b285192aSMauro Carvalho Chehab #define CX18_DEBUG_HI_WARN_DEV(dev, fmt, args...) \
220b285192aSMauro Carvalho Chehab CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_WARN, dev, "warning", fmt , ## args)
221b285192aSMauro Carvalho Chehab #define CX18_DEBUG_HI_INFO_DEV(dev, fmt, args...) \
222b285192aSMauro Carvalho Chehab CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_INFO, dev, "info", fmt , ## args)
223b285192aSMauro Carvalho Chehab #define CX18_DEBUG_HI_API_DEV(dev, fmt, args...) \
224b285192aSMauro Carvalho Chehab CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_API, dev, "api", fmt , ## args)
225b285192aSMauro Carvalho Chehab #define CX18_DEBUG_HI_DMA_DEV(dev, fmt, args...) \
226b285192aSMauro Carvalho Chehab CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_DMA, dev, "dma", fmt , ## args)
227b285192aSMauro Carvalho Chehab #define CX18_DEBUG_HI_IOCTL_DEV(dev, fmt, args...) \
228b285192aSMauro Carvalho Chehab CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_IOCTL, dev, "ioctl", fmt , ## args)
229b285192aSMauro Carvalho Chehab #define CX18_DEBUG_HI_FILE_DEV(dev, fmt, args...) \
230b285192aSMauro Carvalho Chehab CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_FILE, dev, "file", fmt , ## args)
231b285192aSMauro Carvalho Chehab #define CX18_DEBUG_HI_I2C_DEV(dev, fmt, args...) \
232b285192aSMauro Carvalho Chehab CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_I2C, dev, "i2c", fmt , ## args)
233b285192aSMauro Carvalho Chehab #define CX18_DEBUG_HI_IRQ_DEV(dev, fmt, args...) \
234b285192aSMauro Carvalho Chehab CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_IRQ, dev, "irq", fmt , ## args)
235b285192aSMauro Carvalho Chehab
236b285192aSMauro Carvalho Chehab #define CX18_ERR_DEV(dev, fmt, args...) v4l2_err(dev, fmt , ## args)
237b285192aSMauro Carvalho Chehab #define CX18_WARN_DEV(dev, fmt, args...) v4l2_warn(dev, fmt , ## args)
238b285192aSMauro Carvalho Chehab #define CX18_INFO_DEV(dev, fmt, args...) v4l2_info(dev, fmt , ## args)
239b285192aSMauro Carvalho Chehab
240b285192aSMauro Carvalho Chehab extern int cx18_debug;
241b285192aSMauro Carvalho Chehab
242b285192aSMauro Carvalho Chehab struct cx18_options {
243b285192aSMauro Carvalho Chehab int megabytes[CX18_MAX_STREAMS]; /* Size in megabytes of each stream */
244b285192aSMauro Carvalho Chehab int cardtype; /* force card type on load */
245b285192aSMauro Carvalho Chehab int tuner; /* set tuner on load */
246b285192aSMauro Carvalho Chehab int radio; /* enable/disable radio */
247b285192aSMauro Carvalho Chehab };
248b285192aSMauro Carvalho Chehab
249b285192aSMauro Carvalho Chehab /* per-mdl bit flags */
25039c1cb2bSJonathan McCrohan #define CX18_F_M_NEED_SWAP 0 /* mdl buffer data must be endianness swapped */
251b285192aSMauro Carvalho Chehab
252b285192aSMauro Carvalho Chehab /* per-stream, s_flags */
253b285192aSMauro Carvalho Chehab #define CX18_F_S_CLAIMED 3 /* this stream is claimed */
254b285192aSMauro Carvalho Chehab #define CX18_F_S_STREAMING 4 /* the fw is decoding/encoding this stream */
255b285192aSMauro Carvalho Chehab #define CX18_F_S_INTERNAL_USE 5 /* this stream is used internally (sliced VBI processing) */
256b285192aSMauro Carvalho Chehab #define CX18_F_S_STREAMOFF 7 /* signal end of stream EOS */
257b285192aSMauro Carvalho Chehab #define CX18_F_S_APPL_IO 8 /* this stream is used read/written by an application */
258b285192aSMauro Carvalho Chehab #define CX18_F_S_STOPPING 9 /* telling the fw to stop capturing */
259b285192aSMauro Carvalho Chehab
260b285192aSMauro Carvalho Chehab /* per-cx18, i_flags */
261b285192aSMauro Carvalho Chehab #define CX18_F_I_LOADED_FW 0 /* Loaded firmware 1st time */
262b285192aSMauro Carvalho Chehab #define CX18_F_I_EOS 4 /* End of encoder stream */
263b285192aSMauro Carvalho Chehab #define CX18_F_I_RADIO_USER 5 /* radio tuner is selected */
264b285192aSMauro Carvalho Chehab #define CX18_F_I_ENC_PAUSED 13 /* the encoder is paused */
265b285192aSMauro Carvalho Chehab #define CX18_F_I_INITED 21 /* set after first open */
266b285192aSMauro Carvalho Chehab #define CX18_F_I_FAILED 22 /* set if first open failed */
267b285192aSMauro Carvalho Chehab
268b285192aSMauro Carvalho Chehab /* These are the VBI types as they appear in the embedded VBI private packets. */
269b285192aSMauro Carvalho Chehab #define CX18_SLICED_TYPE_TELETEXT_B (1)
270b285192aSMauro Carvalho Chehab #define CX18_SLICED_TYPE_CAPTION_525 (4)
271b285192aSMauro Carvalho Chehab #define CX18_SLICED_TYPE_WSS_625 (5)
272b285192aSMauro Carvalho Chehab #define CX18_SLICED_TYPE_VPS (7)
273b285192aSMauro Carvalho Chehab
274b285192aSMauro Carvalho Chehab /**
275b285192aSMauro Carvalho Chehab * list_entry_is_past_end - check if a previous loop cursor is off list end
276b285192aSMauro Carvalho Chehab * @pos: the type * previously used as a loop cursor.
277b285192aSMauro Carvalho Chehab * @head: the head for your list.
2783943f42cSAndrey Utkin * @member: the name of the list_head within the struct.
279b285192aSMauro Carvalho Chehab *
280b285192aSMauro Carvalho Chehab * Check if the entry's list_head is the head of the list, thus it's not a
281b285192aSMauro Carvalho Chehab * real entry but was the loop cursor that walked past the end
282b285192aSMauro Carvalho Chehab */
283b285192aSMauro Carvalho Chehab #define list_entry_is_past_end(pos, head, member) \
284b285192aSMauro Carvalho Chehab (&pos->member == (head))
285b285192aSMauro Carvalho Chehab
286*643e8350SHans Verkuil struct cx18_vb2_buffer {
287*643e8350SHans Verkuil /* Common video buffer sub-system struct */
288*643e8350SHans Verkuil struct vb2_v4l2_buffer vb;
289*643e8350SHans Verkuil struct list_head list;
290*643e8350SHans Verkuil v4l2_std_id tvnorm; /* selected tv norm */
291*643e8350SHans Verkuil u32 bytes_used;
292*643e8350SHans Verkuil };
293*643e8350SHans Verkuil
294b285192aSMauro Carvalho Chehab struct cx18_buffer {
295b285192aSMauro Carvalho Chehab struct list_head list;
296b285192aSMauro Carvalho Chehab dma_addr_t dma_handle;
297b285192aSMauro Carvalho Chehab char *buf;
298b285192aSMauro Carvalho Chehab
299b285192aSMauro Carvalho Chehab u32 bytesused;
300b285192aSMauro Carvalho Chehab u32 readpos;
301b285192aSMauro Carvalho Chehab };
302b285192aSMauro Carvalho Chehab
303b285192aSMauro Carvalho Chehab struct cx18_mdl {
304b285192aSMauro Carvalho Chehab struct list_head list;
305b285192aSMauro Carvalho Chehab u32 id; /* index into cx->scb->cpu_mdl[] of 1st cx18_mdl_ent */
306b285192aSMauro Carvalho Chehab
307b285192aSMauro Carvalho Chehab unsigned int skipped;
308b285192aSMauro Carvalho Chehab unsigned long m_flags;
309b285192aSMauro Carvalho Chehab
310b285192aSMauro Carvalho Chehab struct list_head buf_list;
311b285192aSMauro Carvalho Chehab struct cx18_buffer *curr_buf; /* current buffer in list for reading */
312b285192aSMauro Carvalho Chehab
313b285192aSMauro Carvalho Chehab u32 bytesused;
314b285192aSMauro Carvalho Chehab u32 readpos;
315b285192aSMauro Carvalho Chehab };
316b285192aSMauro Carvalho Chehab
317b285192aSMauro Carvalho Chehab struct cx18_queue {
318b285192aSMauro Carvalho Chehab struct list_head list;
319b285192aSMauro Carvalho Chehab atomic_t depth;
320b285192aSMauro Carvalho Chehab u32 bytesused;
321b285192aSMauro Carvalho Chehab spinlock_t lock;
322b285192aSMauro Carvalho Chehab };
323b285192aSMauro Carvalho Chehab
324b285192aSMauro Carvalho Chehab struct cx18_stream; /* forward reference */
325b285192aSMauro Carvalho Chehab
326b285192aSMauro Carvalho Chehab struct cx18_dvb {
327b285192aSMauro Carvalho Chehab struct cx18_stream *stream;
328b285192aSMauro Carvalho Chehab struct dmx_frontend hw_frontend;
329b285192aSMauro Carvalho Chehab struct dmx_frontend mem_frontend;
330b285192aSMauro Carvalho Chehab struct dmxdev dmxdev;
331b285192aSMauro Carvalho Chehab struct dvb_adapter dvb_adapter;
332b285192aSMauro Carvalho Chehab struct dvb_demux demux;
333b285192aSMauro Carvalho Chehab struct dvb_frontend *fe;
334b285192aSMauro Carvalho Chehab struct dvb_net dvbnet;
335b285192aSMauro Carvalho Chehab int enabled;
336b285192aSMauro Carvalho Chehab int feeding;
337b285192aSMauro Carvalho Chehab struct mutex feedlock;
338b285192aSMauro Carvalho Chehab };
339b285192aSMauro Carvalho Chehab
340b285192aSMauro Carvalho Chehab struct cx18; /* forward reference */
341b285192aSMauro Carvalho Chehab struct cx18_scb; /* forward reference */
342b285192aSMauro Carvalho Chehab
343b285192aSMauro Carvalho Chehab
344b285192aSMauro Carvalho Chehab #define CX18_MAX_MDL_ACKS 2
345b285192aSMauro Carvalho Chehab #define CX18_MAX_IN_WORK_ORDERS (CX18_MAX_FW_MDLS_PER_STREAM + 7)
346b285192aSMauro Carvalho Chehab /* CPU_DE_RELEASE_MDL can burst CX18_MAX_FW_MDLS_PER_STREAM orders in a group */
347b285192aSMauro Carvalho Chehab
348b285192aSMauro Carvalho Chehab #define CX18_F_EWO_MB_STALE_UPON_RECEIPT 0x1
349b285192aSMauro Carvalho Chehab #define CX18_F_EWO_MB_STALE_WHILE_PROC 0x2
350b285192aSMauro Carvalho Chehab #define CX18_F_EWO_MB_STALE \
351b285192aSMauro Carvalho Chehab (CX18_F_EWO_MB_STALE_UPON_RECEIPT | CX18_F_EWO_MB_STALE_WHILE_PROC)
352b285192aSMauro Carvalho Chehab
353b285192aSMauro Carvalho Chehab struct cx18_in_work_order {
354b285192aSMauro Carvalho Chehab struct work_struct work;
355b285192aSMauro Carvalho Chehab atomic_t pending;
356b285192aSMauro Carvalho Chehab struct cx18 *cx;
357b285192aSMauro Carvalho Chehab unsigned long flags;
358b285192aSMauro Carvalho Chehab int rpu;
359b285192aSMauro Carvalho Chehab struct cx18_mailbox mb;
360b285192aSMauro Carvalho Chehab struct cx18_mdl_ack mdl_ack[CX18_MAX_MDL_ACKS];
361b285192aSMauro Carvalho Chehab char *str;
362b285192aSMauro Carvalho Chehab };
363b285192aSMauro Carvalho Chehab
364b285192aSMauro Carvalho Chehab #define CX18_INVALID_TASK_HANDLE 0xffffffff
365b285192aSMauro Carvalho Chehab
366b285192aSMauro Carvalho Chehab struct cx18_stream {
367b285192aSMauro Carvalho Chehab /* These first five fields are always set, even if the stream
368b285192aSMauro Carvalho Chehab is not actually created. */
36908569d64SHans Verkuil struct video_device video_dev; /* v4l2_dev is NULL when stream not created */
370b285192aSMauro Carvalho Chehab struct cx18_dvb *dvb; /* DVB / Digital Transport */
371b285192aSMauro Carvalho Chehab struct cx18 *cx; /* for ease of use */
372b285192aSMauro Carvalho Chehab const char *name; /* name of the stream */
373b285192aSMauro Carvalho Chehab int type; /* stream type */
374b285192aSMauro Carvalho Chehab u32 handle; /* task handle */
375dfdf780bSHans Verkuil u32 v4l2_dev_caps; /* device capabilities */
376b285192aSMauro Carvalho Chehab unsigned int mdl_base_idx;
377b285192aSMauro Carvalho Chehab
378b285192aSMauro Carvalho Chehab u32 id;
379b285192aSMauro Carvalho Chehab unsigned long s_flags; /* status flags, see above */
380b285192aSMauro Carvalho Chehab int dma; /* can be PCI_DMA_TODEVICE,
381b285192aSMauro Carvalho Chehab PCI_DMA_FROMDEVICE or
382b285192aSMauro Carvalho Chehab PCI_DMA_NONE */
383b285192aSMauro Carvalho Chehab wait_queue_head_t waitq;
384b285192aSMauro Carvalho Chehab
385b285192aSMauro Carvalho Chehab /* Buffers */
386b285192aSMauro Carvalho Chehab struct list_head buf_pool; /* buffers not attached to an MDL */
387b285192aSMauro Carvalho Chehab u32 buffers; /* total buffers owned by this stream */
388b285192aSMauro Carvalho Chehab u32 buf_size; /* size in bytes of a single buffer */
389b285192aSMauro Carvalho Chehab
390b285192aSMauro Carvalho Chehab /* MDL sizes - all stream MDLs are the same size */
391b285192aSMauro Carvalho Chehab u32 bufs_per_mdl;
392b285192aSMauro Carvalho Chehab u32 mdl_size; /* total bytes in all buffers in a mdl */
393b285192aSMauro Carvalho Chehab
394b285192aSMauro Carvalho Chehab /* MDL Queues */
395b285192aSMauro Carvalho Chehab struct cx18_queue q_free; /* free - in rotation, not committed */
396b285192aSMauro Carvalho Chehab struct cx18_queue q_busy; /* busy - in use by firmware */
397b285192aSMauro Carvalho Chehab struct cx18_queue q_full; /* full - data for user apps */
398b285192aSMauro Carvalho Chehab struct cx18_queue q_idle; /* idle - not in rotation */
399b285192aSMauro Carvalho Chehab
400b285192aSMauro Carvalho Chehab struct work_struct out_work_order;
401b285192aSMauro Carvalho Chehab
402b285192aSMauro Carvalho Chehab /* Videobuf for YUV video */
403b285192aSMauro Carvalho Chehab u32 pixelformat;
404b285192aSMauro Carvalho Chehab u32 vb_bytes_per_frame;
40548ab45adSSimon Farnsworth u32 vb_bytes_per_line;
406b285192aSMauro Carvalho Chehab struct list_head vb_capture; /* video capture queue */
407b285192aSMauro Carvalho Chehab spinlock_t vb_lock;
408b285192aSMauro Carvalho Chehab struct timer_list vb_timeout;
409*643e8350SHans Verkuil u32 sequence;
410b285192aSMauro Carvalho Chehab
411*643e8350SHans Verkuil struct vb2_queue vidq;
412b285192aSMauro Carvalho Chehab enum v4l2_buf_type vb_type;
413b285192aSMauro Carvalho Chehab };
414b285192aSMauro Carvalho Chehab
415b285192aSMauro Carvalho Chehab struct cx18_open_id {
416b285192aSMauro Carvalho Chehab struct v4l2_fh fh;
417b285192aSMauro Carvalho Chehab u32 open_id;
418b285192aSMauro Carvalho Chehab int type;
419b285192aSMauro Carvalho Chehab struct cx18 *cx;
420b285192aSMauro Carvalho Chehab };
421b285192aSMauro Carvalho Chehab
fh2id(struct v4l2_fh * fh)422b285192aSMauro Carvalho Chehab static inline struct cx18_open_id *fh2id(struct v4l2_fh *fh)
423b285192aSMauro Carvalho Chehab {
424b285192aSMauro Carvalho Chehab return container_of(fh, struct cx18_open_id, fh);
425b285192aSMauro Carvalho Chehab }
426b285192aSMauro Carvalho Chehab
file2id(struct file * file)427b285192aSMauro Carvalho Chehab static inline struct cx18_open_id *file2id(struct file *file)
428b285192aSMauro Carvalho Chehab {
429b285192aSMauro Carvalho Chehab return fh2id(file->private_data);
430b285192aSMauro Carvalho Chehab }
431b285192aSMauro Carvalho Chehab
432b285192aSMauro Carvalho Chehab /* forward declaration of struct defined in cx18-cards.h */
433b285192aSMauro Carvalho Chehab struct cx18_card;
434b285192aSMauro Carvalho Chehab
435b285192aSMauro Carvalho Chehab /*
436b285192aSMauro Carvalho Chehab * A note about "sliced" VBI data as implemented in this driver:
437b285192aSMauro Carvalho Chehab *
438b285192aSMauro Carvalho Chehab * Currently we collect the sliced VBI in the form of Ancillary Data
439b285192aSMauro Carvalho Chehab * packets, inserted by the AV core decoder/digitizer/slicer in the
440b285192aSMauro Carvalho Chehab * horizontal blanking region of the VBI lines, in "raw" mode as far as
441b285192aSMauro Carvalho Chehab * the Encoder is concerned. We don't ever tell the Encoder itself
442b285192aSMauro Carvalho Chehab * to provide sliced VBI. (AV Core: sliced mode - Encoder: raw mode)
443b285192aSMauro Carvalho Chehab *
444b285192aSMauro Carvalho Chehab * We then process the ancillary data ourselves to send the sliced data
445b285192aSMauro Carvalho Chehab * to the user application directly or build up MPEG-2 private stream 1
446b285192aSMauro Carvalho Chehab * packets to splice into (only!) MPEG-2 PS streams for the user app.
447b285192aSMauro Carvalho Chehab *
448b285192aSMauro Carvalho Chehab * (That's how ivtv essentially does it.)
449b285192aSMauro Carvalho Chehab *
450b285192aSMauro Carvalho Chehab * The Encoder should be able to extract certain sliced VBI data for
451b285192aSMauro Carvalho Chehab * us and provide it in a separate stream or splice it into any type of
452b285192aSMauro Carvalho Chehab * MPEG PS or TS stream, but this isn't implemented yet.
453b285192aSMauro Carvalho Chehab */
454b285192aSMauro Carvalho Chehab
455b285192aSMauro Carvalho Chehab /*
456b285192aSMauro Carvalho Chehab * Number of "raw" VBI samples per horizontal line we tell the Encoder to
457b285192aSMauro Carvalho Chehab * grab from the decoder/digitizer/slicer output for raw or sliced VBI.
458b285192aSMauro Carvalho Chehab * It depends on the pixel clock and the horiz rate:
459b285192aSMauro Carvalho Chehab *
460b285192aSMauro Carvalho Chehab * (1/Fh)*(2*Fp) = Samples/line
461b285192aSMauro Carvalho Chehab * = 4 bytes EAV + Anc data in hblank + 4 bytes SAV + active samples
462b285192aSMauro Carvalho Chehab *
463b285192aSMauro Carvalho Chehab * Sliced VBI data is sent as ancillary data during horizontal blanking
464b285192aSMauro Carvalho Chehab * Raw VBI is sent as active video samples during vertcal blanking
465b285192aSMauro Carvalho Chehab *
466b285192aSMauro Carvalho Chehab * We use a BT.656 pxiel clock of 13.5 MHz and a BT.656 active line
467b285192aSMauro Carvalho Chehab * length of 720 pixels @ 4:2:2 sampling. Thus...
468b285192aSMauro Carvalho Chehab *
469b285192aSMauro Carvalho Chehab * For systems that use a 15.734 kHz horizontal rate, such as
470b285192aSMauro Carvalho Chehab * NTSC-M, PAL-M, PAL-60, and other 60 Hz/525 line systems, we have:
471b285192aSMauro Carvalho Chehab *
472b285192aSMauro Carvalho Chehab * (1/15.734 kHz) * 2 * 13.5 MHz = 1716 samples/line =
473b285192aSMauro Carvalho Chehab * 4 bytes SAV + 268 bytes anc data + 4 bytes SAV + 1440 active samples
474b285192aSMauro Carvalho Chehab *
475b285192aSMauro Carvalho Chehab * For systems that use a 15.625 kHz horizontal rate, such as
476b285192aSMauro Carvalho Chehab * PAL-B/G/H, PAL-I, SECAM-L and other 50 Hz/625 line systems, we have:
477b285192aSMauro Carvalho Chehab *
478b285192aSMauro Carvalho Chehab * (1/15.625 kHz) * 2 * 13.5 MHz = 1728 samples/line =
479b285192aSMauro Carvalho Chehab * 4 bytes SAV + 280 bytes anc data + 4 bytes SAV + 1440 active samples
480b285192aSMauro Carvalho Chehab */
481318de791SMauro Carvalho Chehab #define VBI_ACTIVE_SAMPLES 1444 /* 4 byte SAV + 720 Y + 720 U/V */
482318de791SMauro Carvalho Chehab #define VBI_HBLANK_SAMPLES_60HZ 272 /* 4 byte EAV + 268 anc/fill */
483318de791SMauro Carvalho Chehab #define VBI_HBLANK_SAMPLES_50HZ 284 /* 4 byte EAV + 280 anc/fill */
484b285192aSMauro Carvalho Chehab
485b285192aSMauro Carvalho Chehab #define CX18_VBI_FRAMES 32
486b285192aSMauro Carvalho Chehab
487b285192aSMauro Carvalho Chehab struct vbi_info {
488b285192aSMauro Carvalho Chehab /* Current state of v4l2 VBI settings for this device */
489b285192aSMauro Carvalho Chehab struct v4l2_format in;
490b285192aSMauro Carvalho Chehab struct v4l2_sliced_vbi_format *sliced_in; /* pointer to in.fmt.sliced */
491b285192aSMauro Carvalho Chehab u32 count; /* Count of VBI data lines: 60 Hz: 12 or 50 Hz: 18 */
492b285192aSMauro Carvalho Chehab u32 start[2]; /* First VBI data line per field: 10 & 273 or 6 & 318 */
493b285192aSMauro Carvalho Chehab
494b285192aSMauro Carvalho Chehab u32 frame; /* Count of VBI buffers/frames received from Encoder */
495b285192aSMauro Carvalho Chehab
496b285192aSMauro Carvalho Chehab /*
497b285192aSMauro Carvalho Chehab * Vars for creation and insertion of MPEG Private Stream 1 packets
498b285192aSMauro Carvalho Chehab * of sliced VBI data into an MPEG PS
499b285192aSMauro Carvalho Chehab */
500b285192aSMauro Carvalho Chehab
501b285192aSMauro Carvalho Chehab /* Boolean: create and insert Private Stream 1 packets into the PS */
502b285192aSMauro Carvalho Chehab int insert_mpeg;
503b285192aSMauro Carvalho Chehab
504b285192aSMauro Carvalho Chehab /*
505b285192aSMauro Carvalho Chehab * Buffer for the maximum of 2 * 18 * packet_size sliced VBI lines.
506b285192aSMauro Carvalho Chehab * Used in cx18-vbi.c only for collecting sliced data, and as a source
507b285192aSMauro Carvalho Chehab * during conversion of sliced VBI data into MPEG Priv Stream 1 packets.
508b285192aSMauro Carvalho Chehab * We don't need to save state here, but the array may have been a bit
509b285192aSMauro Carvalho Chehab * too big (2304 bytes) to alloc from the stack.
510b285192aSMauro Carvalho Chehab */
511b285192aSMauro Carvalho Chehab struct v4l2_sliced_vbi_data sliced_data[36];
512b285192aSMauro Carvalho Chehab
513b285192aSMauro Carvalho Chehab /*
514b285192aSMauro Carvalho Chehab * A ring buffer of driver-generated MPEG-2 PS
515b285192aSMauro Carvalho Chehab * Program Pack/Private Stream 1 packets for sliced VBI data insertion
516b285192aSMauro Carvalho Chehab * into the MPEG PS stream.
517b285192aSMauro Carvalho Chehab *
518b285192aSMauro Carvalho Chehab * In each sliced_mpeg_data[] buffer is:
519b285192aSMauro Carvalho Chehab * 16 byte MPEG-2 PS Program Pack Header
520b285192aSMauro Carvalho Chehab * 16 byte MPEG-2 Private Stream 1 PES Header
521b285192aSMauro Carvalho Chehab * 4 byte magic number: "itv0" or "ITV0"
522b285192aSMauro Carvalho Chehab * 4 byte first field line mask, if "itv0"
523b285192aSMauro Carvalho Chehab * 4 byte second field line mask, if "itv0"
524b285192aSMauro Carvalho Chehab * 36 lines, if "ITV0"; or <36 lines, if "itv0"; of sliced VBI data
525b285192aSMauro Carvalho Chehab *
526b285192aSMauro Carvalho Chehab * Each line in the payload is
527b285192aSMauro Carvalho Chehab * 1 byte line header derived from the SDID (WSS, CC, VPS, etc.)
528b285192aSMauro Carvalho Chehab * 42 bytes of line data
529b285192aSMauro Carvalho Chehab *
530b285192aSMauro Carvalho Chehab * That's a maximum 1552 bytes of payload in the Private Stream 1 packet
531b285192aSMauro Carvalho Chehab * which is the payload size a PVR-350 (CX23415) MPEG decoder will
532b285192aSMauro Carvalho Chehab * accept for VBI data. So, including the headers, it's a maximum 1584
533b285192aSMauro Carvalho Chehab * bytes total.
534b285192aSMauro Carvalho Chehab */
535b285192aSMauro Carvalho Chehab #define CX18_SLICED_MPEG_DATA_MAXSZ 1584
536b285192aSMauro Carvalho Chehab /* copy_vbi_buf() needs 8 temp bytes on the end for the worst case */
537b285192aSMauro Carvalho Chehab #define CX18_SLICED_MPEG_DATA_BUFSZ (CX18_SLICED_MPEG_DATA_MAXSZ+8)
538b285192aSMauro Carvalho Chehab u8 *sliced_mpeg_data[CX18_VBI_FRAMES];
539b285192aSMauro Carvalho Chehab u32 sliced_mpeg_size[CX18_VBI_FRAMES];
540b285192aSMauro Carvalho Chehab
541b285192aSMauro Carvalho Chehab /* Count of Program Pack/Program Stream 1 packets inserted into PS */
542b285192aSMauro Carvalho Chehab u32 inserted_frame;
543b285192aSMauro Carvalho Chehab
544b285192aSMauro Carvalho Chehab /*
545b285192aSMauro Carvalho Chehab * A dummy driver stream transfer mdl & buffer with a copy of the next
546b285192aSMauro Carvalho Chehab * sliced_mpeg_data[] buffer for output to userland apps.
547b285192aSMauro Carvalho Chehab * Only used in cx18-fileops.c, but its state needs to persist at times.
548b285192aSMauro Carvalho Chehab */
549b285192aSMauro Carvalho Chehab struct cx18_mdl sliced_mpeg_mdl;
550b285192aSMauro Carvalho Chehab struct cx18_buffer sliced_mpeg_buf;
551b285192aSMauro Carvalho Chehab };
552b285192aSMauro Carvalho Chehab
553b285192aSMauro Carvalho Chehab /* Per cx23418, per I2C bus private algo callback data */
554b285192aSMauro Carvalho Chehab struct cx18_i2c_algo_callback_data {
555b285192aSMauro Carvalho Chehab struct cx18 *cx;
556b285192aSMauro Carvalho Chehab int bus_index; /* 0 or 1 for the cx23418's 1st or 2nd I2C bus */
557b285192aSMauro Carvalho Chehab };
558b285192aSMauro Carvalho Chehab
559b285192aSMauro Carvalho Chehab #define CX18_MAX_MMIO_WR_RETRIES 10
560b285192aSMauro Carvalho Chehab
561b285192aSMauro Carvalho Chehab /* Struct to hold info about cx18 cards */
562b285192aSMauro Carvalho Chehab struct cx18 {
563b285192aSMauro Carvalho Chehab int instance;
564b285192aSMauro Carvalho Chehab struct pci_dev *pci_dev;
565b285192aSMauro Carvalho Chehab struct v4l2_device v4l2_dev;
566b285192aSMauro Carvalho Chehab struct v4l2_subdev *sd_av; /* A/V decoder/digitizer sub-device */
567b285192aSMauro Carvalho Chehab struct v4l2_subdev *sd_extmux; /* External multiplexer sub-dev */
568b285192aSMauro Carvalho Chehab
569b285192aSMauro Carvalho Chehab const struct cx18_card *card; /* card information */
570b285192aSMauro Carvalho Chehab const char *card_name; /* full name of the card */
571b285192aSMauro Carvalho Chehab const struct cx18_card_tuner_i2c *card_i2c; /* i2c addresses to probe for tuner */
572b285192aSMauro Carvalho Chehab u8 is_50hz;
573b285192aSMauro Carvalho Chehab u8 is_60hz;
574b285192aSMauro Carvalho Chehab u8 nof_inputs; /* number of video inputs */
575b285192aSMauro Carvalho Chehab u8 nof_audio_inputs; /* number of audio inputs */
576b285192aSMauro Carvalho Chehab u32 v4l2_cap; /* V4L2 capabilities of card */
577b285192aSMauro Carvalho Chehab u32 hw_flags; /* Hardware description of the board */
578b285192aSMauro Carvalho Chehab unsigned int free_mdl_idx;
579b285192aSMauro Carvalho Chehab struct cx18_scb __iomem *scb; /* pointer to SCB */
580b285192aSMauro Carvalho Chehab struct mutex epu2apu_mb_lock; /* protect driver to chip mailbox in SCB*/
581b285192aSMauro Carvalho Chehab struct mutex epu2cpu_mb_lock; /* protect driver to chip mailbox in SCB*/
582b285192aSMauro Carvalho Chehab
583b285192aSMauro Carvalho Chehab struct cx18_av_state av_state;
584b285192aSMauro Carvalho Chehab
585b285192aSMauro Carvalho Chehab /* codec settings */
586b285192aSMauro Carvalho Chehab struct cx2341x_handler cxhdl;
587b285192aSMauro Carvalho Chehab u32 filter_mode;
588b285192aSMauro Carvalho Chehab u32 temporal_strength;
589b285192aSMauro Carvalho Chehab u32 spatial_strength;
590b285192aSMauro Carvalho Chehab
591b285192aSMauro Carvalho Chehab /* dualwatch */
592b285192aSMauro Carvalho Chehab unsigned long dualwatch_jiffies;
593b285192aSMauro Carvalho Chehab u32 dualwatch_stereo_mode;
594b285192aSMauro Carvalho Chehab
595b285192aSMauro Carvalho Chehab struct mutex serialize_lock; /* mutex used to serialize open/close/start/stop/ioctl operations */
596b285192aSMauro Carvalho Chehab struct cx18_options options; /* User options */
597b285192aSMauro Carvalho Chehab int stream_buffers[CX18_MAX_STREAMS]; /* # of buffers for each stream */
598b285192aSMauro Carvalho Chehab int stream_buf_size[CX18_MAX_STREAMS]; /* Stream buffer size */
599b285192aSMauro Carvalho Chehab struct cx18_stream streams[CX18_MAX_STREAMS]; /* Stream data */
600b285192aSMauro Carvalho Chehab struct snd_cx18_card *alsa; /* ALSA interface for PCM capture stream */
601b285192aSMauro Carvalho Chehab void (*pcm_announce_callback)(struct snd_cx18_card *card, u8 *pcm_data,
602b285192aSMauro Carvalho Chehab size_t num_bytes);
603b285192aSMauro Carvalho Chehab
604b285192aSMauro Carvalho Chehab unsigned long i_flags; /* global cx18 flags */
605b285192aSMauro Carvalho Chehab atomic_t ana_capturing; /* count number of active analog capture streams */
606b285192aSMauro Carvalho Chehab atomic_t tot_capturing; /* total count number of active capture streams */
607b285192aSMauro Carvalho Chehab int search_pack_header;
608b285192aSMauro Carvalho Chehab
609b285192aSMauro Carvalho Chehab int open_id; /* incremented each time an open occurs, used as
610b285192aSMauro Carvalho Chehab unique ID. Starts at 1, so 0 can be used as
611b285192aSMauro Carvalho Chehab uninitialized value in the stream->id. */
612b285192aSMauro Carvalho Chehab
613b285192aSMauro Carvalho Chehab resource_size_t base_addr;
614b285192aSMauro Carvalho Chehab
615b285192aSMauro Carvalho Chehab u8 card_rev;
616b285192aSMauro Carvalho Chehab void __iomem *enc_mem, *reg_mem;
617b285192aSMauro Carvalho Chehab
618b285192aSMauro Carvalho Chehab struct vbi_info vbi;
619b285192aSMauro Carvalho Chehab
620b285192aSMauro Carvalho Chehab u64 mpg_data_received;
621b285192aSMauro Carvalho Chehab u64 vbi_data_inserted;
622b285192aSMauro Carvalho Chehab
623b285192aSMauro Carvalho Chehab wait_queue_head_t mb_apu_waitq;
624b285192aSMauro Carvalho Chehab wait_queue_head_t mb_cpu_waitq;
625b285192aSMauro Carvalho Chehab wait_queue_head_t cap_w;
626b285192aSMauro Carvalho Chehab /* when the current DMA is finished this queue is woken up */
627b285192aSMauro Carvalho Chehab wait_queue_head_t dma_waitq;
628b285192aSMauro Carvalho Chehab
629b285192aSMauro Carvalho Chehab u32 sw1_irq_mask;
630b285192aSMauro Carvalho Chehab u32 sw2_irq_mask;
631b285192aSMauro Carvalho Chehab u32 hw2_irq_mask;
632b285192aSMauro Carvalho Chehab
633b285192aSMauro Carvalho Chehab struct workqueue_struct *in_work_queue;
634b285192aSMauro Carvalho Chehab char in_workq_name[11]; /* "cx18-NN-in" */
635b285192aSMauro Carvalho Chehab struct cx18_in_work_order in_work_order[CX18_MAX_IN_WORK_ORDERS];
636b285192aSMauro Carvalho Chehab char epu_debug_str[256]; /* CX18_EPU_DEBUG is rare: use shared space */
637b285192aSMauro Carvalho Chehab
638b285192aSMauro Carvalho Chehab /* i2c */
639b285192aSMauro Carvalho Chehab struct i2c_adapter i2c_adap[2];
640b285192aSMauro Carvalho Chehab struct i2c_algo_bit_data i2c_algo[2];
641b285192aSMauro Carvalho Chehab struct cx18_i2c_algo_callback_data i2c_algo_cb_data[2];
642b285192aSMauro Carvalho Chehab
643b285192aSMauro Carvalho Chehab struct IR_i2c_init_data ir_i2c_init_data;
644b285192aSMauro Carvalho Chehab
645b285192aSMauro Carvalho Chehab /* gpio */
646b285192aSMauro Carvalho Chehab u32 gpio_dir;
647b285192aSMauro Carvalho Chehab u32 gpio_val;
648b285192aSMauro Carvalho Chehab struct mutex gpio_lock;
649b285192aSMauro Carvalho Chehab struct v4l2_subdev sd_gpiomux;
650b285192aSMauro Carvalho Chehab struct v4l2_subdev sd_resetctrl;
651b285192aSMauro Carvalho Chehab
652b285192aSMauro Carvalho Chehab /* v4l2 and User settings */
653b285192aSMauro Carvalho Chehab
654b285192aSMauro Carvalho Chehab /* codec settings */
655b285192aSMauro Carvalho Chehab u32 audio_input;
656b285192aSMauro Carvalho Chehab u32 active_input;
657b285192aSMauro Carvalho Chehab v4l2_std_id std;
658b285192aSMauro Carvalho Chehab v4l2_std_id tuner_std; /* The norm of the tuner (fixed) */
659b285192aSMauro Carvalho Chehab
660b285192aSMauro Carvalho Chehab /* Used for cx18-alsa module loading */
661b285192aSMauro Carvalho Chehab struct work_struct request_module_wk;
662b285192aSMauro Carvalho Chehab };
663b285192aSMauro Carvalho Chehab
to_cx18(struct v4l2_device * v4l2_dev)664b285192aSMauro Carvalho Chehab static inline struct cx18 *to_cx18(struct v4l2_device *v4l2_dev)
665b285192aSMauro Carvalho Chehab {
666b285192aSMauro Carvalho Chehab return container_of(v4l2_dev, struct cx18, v4l2_dev);
667b285192aSMauro Carvalho Chehab }
668b285192aSMauro Carvalho Chehab
669b285192aSMauro Carvalho Chehab /* cx18 extensions to be loaded */
670b285192aSMauro Carvalho Chehab extern int (*cx18_ext_init)(struct cx18 *);
671b285192aSMauro Carvalho Chehab
672b285192aSMauro Carvalho Chehab /* Globals */
673b285192aSMauro Carvalho Chehab extern int cx18_first_minor;
674b285192aSMauro Carvalho Chehab
675b285192aSMauro Carvalho Chehab /*==============Prototypes==================*/
676b285192aSMauro Carvalho Chehab
677b285192aSMauro Carvalho Chehab /* Return non-zero if a signal is pending */
678b285192aSMauro Carvalho Chehab int cx18_msleep_timeout(unsigned int msecs, int intr);
679b285192aSMauro Carvalho Chehab
680b285192aSMauro Carvalho Chehab /* Read Hauppauge eeprom */
681b285192aSMauro Carvalho Chehab struct tveeprom; /* forward reference */
682b285192aSMauro Carvalho Chehab void cx18_read_eeprom(struct cx18 *cx, struct tveeprom *tv);
683b285192aSMauro Carvalho Chehab
684b285192aSMauro Carvalho Chehab /* First-open initialization: load firmware, etc. */
685b285192aSMauro Carvalho Chehab int cx18_init_on_first_open(struct cx18 *cx);
686b285192aSMauro Carvalho Chehab
687b285192aSMauro Carvalho Chehab /* Test if the current VBI mode is raw (1) or sliced (0) */
cx18_raw_vbi(const struct cx18 * cx)688b285192aSMauro Carvalho Chehab static inline int cx18_raw_vbi(const struct cx18 *cx)
689b285192aSMauro Carvalho Chehab {
690b285192aSMauro Carvalho Chehab return cx->vbi.in.type == V4L2_BUF_TYPE_VBI_CAPTURE;
691b285192aSMauro Carvalho Chehab }
692b285192aSMauro Carvalho Chehab
693b285192aSMauro Carvalho Chehab /* Call the specified callback for all subdevs with a grp_id bit matching the
694b285192aSMauro Carvalho Chehab * mask in hw (if 0, then match them all). Ignore any errors. */
695b285192aSMauro Carvalho Chehab #define cx18_call_hw(cx, hw, o, f, args...) \
696fe293011SHans Verkuil v4l2_device_mask_call_all(&(cx)->v4l2_dev, hw, o, f, ##args)
697b285192aSMauro Carvalho Chehab
698b285192aSMauro Carvalho Chehab #define cx18_call_all(cx, o, f, args...) cx18_call_hw(cx, 0, o, f , ##args)
699b285192aSMauro Carvalho Chehab
700b285192aSMauro Carvalho Chehab /* Call the specified callback for all subdevs with a grp_id bit matching the
701b285192aSMauro Carvalho Chehab * mask in hw (if 0, then match them all). If the callback returns an error
702b285192aSMauro Carvalho Chehab * other than 0 or -ENOIOCTLCMD, then return with that error code. */
703b285192aSMauro Carvalho Chehab #define cx18_call_hw_err(cx, hw, o, f, args...) \
704fe293011SHans Verkuil v4l2_device_mask_call_until_err(&(cx)->v4l2_dev, hw, o, f, ##args)
705b285192aSMauro Carvalho Chehab
706b285192aSMauro Carvalho Chehab #define cx18_call_all_err(cx, o, f, args...) \
707b285192aSMauro Carvalho Chehab cx18_call_hw_err(cx, 0, o, f , ##args)
708b285192aSMauro Carvalho Chehab
709b285192aSMauro Carvalho Chehab #endif /* CX18_DRIVER_H */
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