| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | spi-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
13 need to be defined in the peripheral node because they are per-peripheral and
19 - Mark Brown <broonie@kernel.org>
27 - minimum: 0
32 spi-cs-high:
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| /openbmc/linux/Documentation/admin-guide/mm/ |
| H A D | userfaultfd.rst | 8 Userfaults allow the implementation of on-demand paging from userland
38 Vmas are not suitable for page- (or hugepage) granular fault tracking
48 is a corner case that would currently return ``-EBUSY``).
54 ----------------------
63 - Any user can always create a userfaultfd which traps userspace page faults
67 - In order to also trap kernel page faults for the address space, either the
84 --------------------------
101 - The ``UFFD_FEATURE_EVENT_*`` flags indicate that various other events
103 detail below in the `Non-cooperative userfaultfd`_ section.
105 - ``UFFD_FEATURE_MISSING_HUGETLBFS`` and ``UFFD_FEATURE_MISSING_SHMEM``
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| /openbmc/linux/arch/sh/kernel/cpu/sh4a/ |
| H A D | perf_event.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Performance events support for SH-4A performance counters
24 * The PMCAT location for SH-X3 CPUs was quietly moved, while the CCBR
28 * Early cuts of SH-X3 still appear to use the SH-X/SH-X2 locations, and
59 * ---------- -----------
65 * 0x0203 instruction execution in parallel
72 * 0x0028 number of accesses to instruction memories
76 * 0x0030 number of reads to operand memories
77 * 0x0038 number of writes to operand memories
102 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0029, /* I-cache */
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| /openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | sama5d2.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Chip-specific header file for the SAMA5D2 SoC
29 #define ATMEL_ID_MATRIX1 14 /* H32MX, 32-bit AHB Matrix */
30 #define ATMEL_ID_MATRIX0 15 /* H64MX, 64-bit AHB Matrix */
32 #define ATMEL_ID_HSMC 17 /* Multi-bit ECC interrupt */
33 #define ATMEL_ID_PIOA 18 /* Parallel I/O Controller A */
44 #define ATMEL_ID_TWIHS0 29 /* Two-wire Interface 0 */
45 #define ATMEL_ID_TWIHS1 30 /* Two-wire Interface 1 */
69 #define ATMEL_ID_I2SC0 54 /* Inter-IC Sound Controller 0 */
70 #define ATMEL_ID_I2SC1 55 /* Inter-IC Sound Controller 1 */
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| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Raw/Parallel NAND Device Support"
7 This enables support for accessing all type of raw/parallel
9 <http://www.linux-mtd.infradead.org/doc/nand.html>.
13 comment "Raw/parallel NAND flash controllers"
126 include NAND flash controllers with built-in hardware ECC
161 - PXA3xx processors (NFCv1)
162 - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2)
163 - 64-bit Aramda platforms (7k, 8k, ac5) (NFCv2)
203 BCMA bus can have various flash memories attached, they are
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| /openbmc/linux/Documentation/driver-api/ |
| H A D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
19 output 4 and 8 bits each (x4, x8). Grouping several of these in parallel
26 parallel. In general, this is the Field Replaceable Unit (FRU) which
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
56 one 64 bits parallel access. Typically used with SDR, DDR, DDR2 and DDR3
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
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| /openbmc/linux/sound/drivers/ |
| H A D | mtpav.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * -------
20 * PC Parallel Port ( which this driver currently uses )
23 * -------------
26 * 128 'scene' memories, recallable from MIDI program change
30 * - Recoded & debugged
31 * - Added timer interrupt for midi outputs
32 * - hwports is between 1 and 8, which specifies the number of hardware ports.
66 static int hwports = MTPAV_MAX_PORTS; /* use hardware ports 1-8 */
73 MODULE_PARM_DESC(port, "Parallel port # for MotuMTPAV MIDI.");
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| /openbmc/linux/Documentation/block/ |
| H A D | blk-mq.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Multi-Queue Block IO Queueing Mechanism (blk-mq)
7 The Multi-Queue Block IO Queueing Mechanism is an API to enable fast storage
16 ----------
26 However, with the development of Solid State Drives and Non-Volatile Memories
28 high parallel access, the bottleneck of the stack had moved from the storage
30 in those devices' design, the multi-queue mechanism was introduced.
36 to different CPUs) wanted to perform block IO. Instead of this, the blk-mq API
42 ---------
45 for instance), blk-mq takes action: it will store and manage IO requests to
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| /openbmc/u-boot/drivers/spi/ |
| H A D | Kconfig | 16 typically use driver-private data instead of extending the
23 This extension is meant to simplify interaction with SPI memories
24 by providing an high-level interface to send memory-like commands.
65 please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
94 Enable the Broadcom set-top box SPI driver. This driver can
101 Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
178 to access the SPI NOR flash, MMC-over-SPI on platforms based on
215 for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c.
218 #address-cells = <1>;
219 #size-cells = <0>;
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| /openbmc/linux/drivers/bus/ |
| H A D | qcom-ebi2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * an older version of the Qualcomm Parallel Interface Controller (QPIC)
41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42 * memory continues to drive the data bus after OE is de-asserted.
45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
55 * Bits 3-0: RD_WAIT number of wait cycles for every read access, 0=1 cycle
74 * Bits 31-28: ?
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| /openbmc/linux/drivers/spi/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
55 This extension is meant to simplify interaction with SPI memories
56 by providing a high-level interface to send memory-like commands.
145 supports spi-mem interface.
222 Select this to get SPI support through I/O pins (GPIO, parallel
224 this code to manage the per-word or per-transfer accesses to the
232 tristate "Parallel port adapter for AVR Butterfly (DEVELOPMENT)"
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| /openbmc/qemu/system/ |
| H A D | vl.c | 4 * Copyright (c) 2003-2008 Fabrice Bellard
26 #include "qemu/help-texts.h"
29 #include "exec/cpu-common.h"
30 #include "exec/page-vary.h"
31 #include "hw/qdev-properties.h"
32 #include "qapi/compat-policy.h"
37 #include "qemu-version.h"
40 #include "qemu/hw-version.h"
44 #include "sysemu/runstate-action.h"
49 #include "qemu/error-report.h"
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| /openbmc/linux/drivers/infiniband/hw/qib/ |
| H A D | qib_sd7220.c | 3 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
117 * Below keeps track of whether the "once per power-on" initialization has
126 struct qib_devdata *dd = ppd->dd; in qib_ibsd_ucode_loaded()
128 if (!dd->cspec->serdes_first_init_done && in qib_ibsd_ucode_loaded()
130 dd->cspec->serdes_first_init_done = 1; in qib_ibsd_ucode_loaded()
131 return dd->cspec->serdes_first_init_done; in qib_ibsd_ucode_loaded()
147 /* clear, then re-enable parity errs */ in qib_sd7220_clr_ibpar()
168 * to be re-synchronized, between the host and the uC.
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dce_calcs.c | 38 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
42 * remain as-is as it provides us with a guarantee from HW that it is correct.
141 yclk[low] = vbios->low_yclk; in calculate_bandwidth()
142 yclk[mid] = vbios->mid_yclk; in calculate_bandwidth()
143 yclk[high] = vbios->high_yclk; in calculate_bandwidth()
144 sclk[s_low] = vbios->low_sclk; in calculate_bandwidth()
145 sclk[s_mid1] = vbios->mid1_sclk; in calculate_bandwidth()
146 sclk[s_mid2] = vbios->mid2_sclk; in calculate_bandwidth()
147 sclk[s_mid3] = vbios->mid3_sclk; in calculate_bandwidth()
148 sclk[s_mid4] = vbios->mid4_sclk; in calculate_bandwidth()
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| /openbmc/linux/drivers/mtd/spi-nor/ |
| H A D | core.c | 1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mtd/spi-nor.h>
30 * For everything but full-chip erase; probably could be much smaller, but kept
36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
47 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
60 switch (nor->cmd_ext_type) { in spi_nor_get_cmd_ext()
62 return ~op->cmd.opcode; in spi_nor_get_cmd_ext()
65 return op->cmd.opcode; in spi_nor_get_cmd_ext()
68 dev_err(nor->dev, "Unknown command extension type\n"); in spi_nor_get_cmd_ext()
74 * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op.
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| /openbmc/linux/drivers/accel/habanalabs/gaudi/ |
| H A D | gaudi.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2022 HabanaLabs, Ltd.
27 * - Range registers
28 * - MMU
31 * - Range registers (protect the first 512MB)
34 * - Range registers
35 * - Protection bits
40 * - DMA is not secured.
41 * - PQ and CQ are secured.
42 * - CP is secured: The driver needs to parse CB but WREG should be allowed
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| /openbmc/linux/arch/m68k/kernel/ |
| H A D | head.S | 1 /* -*- mode: asm -*-
3 ** head.S -- This file contains the initial boot code for the
19 ** ++ Bjoern & Roman: ATARI-68040 support for the Medusa
22 ** Magnum- and FX-alternate ram
25 ** for linux-2.1.115
49 * . Enable cache memories
53 * 1) Remove register dependency through-out the file.
61 * write-ups on the structure of the file, and the features of the
65 * ------------------
74 * actual per-machine specific code very simple.
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| /openbmc/linux/drivers/accel/habanalabs/common/ |
| H A D | habanalabs.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2022 HabanaLabs, Ltd.
19 #include <linux/dma-direction.h>
28 #include <linux/io-64-nonatomic-lo-hi.h>
30 #include <linux/dma-buf.h>
42 * bits[63:59] - Encode mmap type
43 * bits[45:0] - mmap offset value
48 #define HL_MMAP_TYPE_SHIFT (59 - PAGE_SHIFT)
107 * enum hl_mmu_page_table_location - mmu page table location
108 * @MMU_DR_PGT: page-table is located on device DRAM.
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| /openbmc/linux/drivers/net/wireless/atmel/ |
| H A D | atmel.c | 1 /*** -*- linux-c -*- **********************************************************
5 Copyright 2000-2001 ATMEL Corporation.
6 Copyright 2003-2004 Simon Kelley.
80 over-rides any automatic selection */
100 MODULE_FIRMWARE("atmel_at76c502-wpa.bin");
102 MODULE_FIRMWARE("atmel_at76c502d-wpa.bin");
104 MODULE_FIRMWARE("atmel_at76c502e-wpa.bin");
106 MODULE_FIRMWARE("atmel_at76c502_3com-wpa.bin");
108 MODULE_FIRMWARE("atmel_at76c504-wpa.bin");
110 MODULE_FIRMWARE("atmel_at76c504_2958-wpa.bin");
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| /openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/ |
| H A D | bnx2x_main.c | 3 * Copyright (c) 2007-2013 Broadcom Corporation
36 #include <linux/dma-mapping.h>
83 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
84 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
85 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
86 #define FW_FILE_NAME_E1_V15 "bnx2x/bnx2x-e1-" FW_FILE_VERSION_V15 ".fw"
87 #define FW_FILE_NAME_E1H_V15 "bnx2x/bnx2x-e1h-" FW_FILE_VERSION_V15 ".fw"
88 #define FW_FILE_NAME_E2_V15 "bnx2x/bnx2x-e2-" FW_FILE_VERSION_V15 ".fw"
117 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
124 static int mrrs = -1;
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| /openbmc/linux/drivers/infiniband/hw/hfi1/ |
| H A D | chip.c | 1 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
3 * Copyright(c) 2015 - 2020 Intel Corporation.
32 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
78 #define SEC_SC_HALTED 0x4 /* per-context only */
79 #define SEC_SPC_FREEZE 0x8 /* per-HFI only */
87 * 0 - User Fecn Handling
88 * 1 - Vnic
89 * 2 - AIP
90 * 3 - Verbs
101 #define emulator_rev(dd) ((dd)->irev >> 8)
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