xref: /openbmc/linux/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e)
18762b07cSPratyush Yadav# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
28762b07cSPratyush Yadav%YAML 1.2
38762b07cSPratyush Yadav---
48762b07cSPratyush Yadav$id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
58762b07cSPratyush Yadav$schema: http://devicetree.org/meta-schemas/core.yaml#
68762b07cSPratyush Yadav
78762b07cSPratyush Yadavtitle: Peripheral-specific properties for a SPI bus.
88762b07cSPratyush Yadav
98762b07cSPratyush Yadavdescription:
108762b07cSPratyush Yadav  Many SPI controllers need to add properties to peripheral devices. They could
118762b07cSPratyush Yadav  be common properties like spi-max-frequency, spi-cpha, etc. or they could be
128762b07cSPratyush Yadav  controller specific like delay in clock or data lines, etc. These properties
138762b07cSPratyush Yadav  need to be defined in the peripheral node because they are per-peripheral and
148762b07cSPratyush Yadav  there can be multiple peripherals attached to a controller. All those
158762b07cSPratyush Yadav  properties are listed here. The controller specific properties should go in
168762b07cSPratyush Yadav  their own separate schema that should be referenced from here.
178762b07cSPratyush Yadav
188762b07cSPratyush Yadavmaintainers:
192fd92c7bSKrzysztof Kozlowski  - Mark Brown <broonie@kernel.org>
208762b07cSPratyush Yadav
218762b07cSPratyush Yadavproperties:
228762b07cSPratyush Yadav  reg:
238762b07cSPratyush Yadav    minItems: 1
248762b07cSPratyush Yadav    maxItems: 256
258762b07cSPratyush Yadav    items:
2660b1e971SRob Herring      items:
2760b1e971SRob Herring        - minimum: 0
288762b07cSPratyush Yadav          maximum: 256
298762b07cSPratyush Yadav    description:
308762b07cSPratyush Yadav      Chip select used by the device.
318762b07cSPratyush Yadav
328762b07cSPratyush Yadav  spi-cs-high:
338762b07cSPratyush Yadav    $ref: /schemas/types.yaml#/definitions/flag
348762b07cSPratyush Yadav    description:
358762b07cSPratyush Yadav      The device requires the chip select active high.
368762b07cSPratyush Yadav
378762b07cSPratyush Yadav  spi-lsb-first:
388762b07cSPratyush Yadav    $ref: /schemas/types.yaml#/definitions/flag
398762b07cSPratyush Yadav    description:
408762b07cSPratyush Yadav      The device requires the LSB first mode.
418762b07cSPratyush Yadav
428762b07cSPratyush Yadav  spi-max-frequency:
438762b07cSPratyush Yadav    $ref: /schemas/types.yaml#/definitions/uint32
448762b07cSPratyush Yadav    description:
458762b07cSPratyush Yadav      Maximum SPI clocking speed of the device in Hz.
468762b07cSPratyush Yadav
4738892ea4SHector Martin  spi-cs-setup-delay-ns:
48f6c911f3STudor Ambarus    description:
4938892ea4SHector Martin      Delay in nanoseconds to be introduced by the controller after CS is
50f6c911f3STudor Ambarus      asserted.
51f6c911f3STudor Ambarus
52*34f89f23SJanne Grunau  spi-cs-hold-delay-ns:
53*34f89f23SJanne Grunau    description:
54*34f89f23SJanne Grunau      Delay in nanoseconds to be introduced by the controller before CS is
55*34f89f23SJanne Grunau      de-asserted.
56*34f89f23SJanne Grunau
57*34f89f23SJanne Grunau  spi-cs-inactive-delay-ns:
58*34f89f23SJanne Grunau    description:
59*34f89f23SJanne Grunau      Delay in nanoseconds to be introduced by the controller after CS is
60*34f89f23SJanne Grunau      de-asserted.
61*34f89f23SJanne Grunau
628762b07cSPratyush Yadav  spi-rx-bus-width:
638762b07cSPratyush Yadav    description:
648762b07cSPratyush Yadav      Bus width to the SPI bus used for read transfers.
658762b07cSPratyush Yadav      If 0 is provided, then no RX will be possible on this device.
668762b07cSPratyush Yadav    $ref: /schemas/types.yaml#/definitions/uint32
678762b07cSPratyush Yadav    enum: [0, 1, 2, 4, 8]
688762b07cSPratyush Yadav    default: 1
698762b07cSPratyush Yadav
708762b07cSPratyush Yadav  spi-rx-delay-us:
718762b07cSPratyush Yadav    description:
728762b07cSPratyush Yadav      Delay, in microseconds, after a read transfer.
738762b07cSPratyush Yadav
74b658be56SRob Herring  rx-sample-delay-ns:
75b658be56SRob Herring    description: SPI Rx sample delay offset, unit is nanoseconds.
76b658be56SRob Herring      The delay from the default sample time before the actual
77b658be56SRob Herring      sample of the rxd input signal occurs.
78b658be56SRob Herring
798762b07cSPratyush Yadav  spi-tx-bus-width:
808762b07cSPratyush Yadav    description:
818762b07cSPratyush Yadav      Bus width to the SPI bus used for write transfers.
828762b07cSPratyush Yadav      If 0 is provided, then no TX will be possible on this device.
838762b07cSPratyush Yadav    $ref: /schemas/types.yaml#/definitions/uint32
848762b07cSPratyush Yadav    enum: [0, 1, 2, 4, 8]
858762b07cSPratyush Yadav    default: 1
868762b07cSPratyush Yadav
878762b07cSPratyush Yadav  spi-tx-delay-us:
888762b07cSPratyush Yadav    description:
898762b07cSPratyush Yadav      Delay, in microseconds, after a write transfer.
908762b07cSPratyush Yadav
91e2edd1b6SMiquel Raynal  stacked-memories:
92e2edd1b6SMiquel Raynal    description: Several SPI memories can be wired in stacked mode.
93e2edd1b6SMiquel Raynal      This basically means that either a device features several chip
94e2edd1b6SMiquel Raynal      selects, or that different devices must be seen as a single
95e2edd1b6SMiquel Raynal      bigger chip. This basically doubles (or more) the total address
96e2edd1b6SMiquel Raynal      space with only a single additional wire, while still needing
97e2edd1b6SMiquel Raynal      to repeat the commands when crossing a chip boundary. The size of
98e2edd1b6SMiquel Raynal      each chip should be provided as members of the array.
99e2edd1b6SMiquel Raynal    $ref: /schemas/types.yaml#/definitions/uint64-array
100e2edd1b6SMiquel Raynal    minItems: 2
101e2edd1b6SMiquel Raynal    maxItems: 4
102e2edd1b6SMiquel Raynal
103e2edd1b6SMiquel Raynal  parallel-memories:
104e2edd1b6SMiquel Raynal    description: Several SPI memories can be wired in parallel mode.
105e2edd1b6SMiquel Raynal      The devices are physically on a different buses but will always
106e2edd1b6SMiquel Raynal      act synchronously as each data word is spread across the
107e2edd1b6SMiquel Raynal      different memories (eg. even bits are stored in one memory, odd
108e2edd1b6SMiquel Raynal      bits in the other). This basically doubles the address space and
109e2edd1b6SMiquel Raynal      the throughput while greatly complexifying the wiring because as
110e2edd1b6SMiquel Raynal      many busses as devices must be wired. The size of each chip should
111e2edd1b6SMiquel Raynal      be provided as members of the array.
112e2edd1b6SMiquel Raynal    $ref: /schemas/types.yaml#/definitions/uint64-array
113e2edd1b6SMiquel Raynal    minItems: 2
114e2edd1b6SMiquel Raynal    maxItems: 4
115e2edd1b6SMiquel Raynal
1168762b07cSPratyush Yadav# The controller specific properties go here.
117b6bdc6e0SPratyush YadavallOf:
118b6bdc6e0SPratyush Yadav  - $ref: cdns,qspi-nor-peripheral-props.yaml#
1190ff4827eSKrzysztof Kozlowski  - $ref: samsung,spi-peripheral-props.yaml#
120e2391782SKrishna Yarlagadda  - $ref: nvidia,tegra210-quad-peripheral-props.yaml#
1218762b07cSPratyush Yadav
1228762b07cSPratyush YadavadditionalProperties: true
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