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/openbmc/linux/Documentation/mm/
H A Dpage_tables.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Page Tables
10 feature of all Unix-like systems as time went by. In 1985 the feature was
13 Page tables map virtual addresses as seen by the CPU into physical addresses
16 Linux defines page tables as a hierarchy which is currently five levels in
21 by the underlying physical page frame. The **page frame number** or **pfn**
22 is the physical address of the page (as seen on the external memory bus)
26 the last page of physical memory the external address bus of the CPU can
29 With a page granularity of 4KB and a address range of 32 bits, pfn 0 is at
34 As you can see, with 4KB pages the page base address uses bits 12-31 of the
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H A Dvmemmap_dedup.rst2 .. SPDX-License-Identifier: GPL-2.0
13 The ``struct page`` structures are used to describe a physical page frame. By
14 default, there is a one-to-one mapping from a page frame to its corresponding
15 ``struct page``.
17 HugeTLB pages consist of multiple base page size pages and is supported by many
18 architectures. See Documentation/admin-guide/mm/hugetlbpage.rst for more
19 details. On the x86-64 architecture, HugeTLB pages of size 2MB and 1GB are
20 currently supported. Since the base page size on x86 is 4KB, a 2MB HugeTLB page
21 consists of 512 base pages and a 1GB HugeTLB page consists of 262144 base pages.
22 For each base page, there is a corresponding ``struct page``.
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/openbmc/linux/arch/x86/kvm/mmu/
H A Dtdp_iter.c1 // SPDX-License-Identifier: GPL-2.0
9 * Recalculates the pointer to the SPTE for the current GFN and level and
14 iter->sptep = iter->pt_path[iter->level - 1] + in tdp_iter_refresh_sptep()
15 SPTE_INDEX(iter->gfn << PAGE_SHIFT, iter->level); in tdp_iter_refresh_sptep()
16 iter->old_spte = kvm_tdp_mmu_read_spte(iter->sptep); in tdp_iter_refresh_sptep()
25 iter->yielded = false; in tdp_iter_restart()
26 iter->yielded_gfn = iter->next_last_level_gfn; in tdp_iter_restart()
27 iter->level = iter->root_level; in tdp_iter_restart()
29 iter->gfn = gfn_round_for_level(iter->next_last_level_gfn, iter->level); in tdp_iter_restart()
32 iter->valid = true; in tdp_iter_restart()
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H A Dpaging_tmpl.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
19 * The MMU needs to be able to access/walk 32-bit and 64-bit guest page tables,
21 * once per guest PTE type. The per-type defines are #undef'd at the end.
50 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
58 #define PT_HAVE_ACCESSED_DIRTY(mmu) (!(mmu)->cpu_role.base.ad_disabled)
64 /* Common logic, but per-type values. These also need to be undefined. */
65 #define PT_BASE_ADDR_MASK ((pt_element_t)(((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)))
77 * The guest_walker structure emulates the behavior of the hardware page
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H A Dmmu_internal.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 /* Page table builder macros common to shadow (host) PTEs and guest PTEs. */
16 #define __PT_LEVEL_SHIFT(level, bits_per_level) \ argument
17 (PAGE_SHIFT + ((level) - 1) * (bits_per_level))
18 #define __PT_INDEX(address, level, bits_per_level) \ argument
19 (((address) >> __PT_LEVEL_SHIFT(level, bits_per_level)) & ((1 << (bits_per_level)) - 1))
21 #define __PT_LVL_ADDR_MASK(base_addr_mask, level, bits_per_level) \ argument
22 ((base_addr_mask) & ~((1ULL << (PAGE_SHIFT + (((level) - 1) * (bits_per_level)))) - 1))
24 #define __PT_LVL_OFFSET_MASK(base_addr_mask, level, bits_per_level) \ argument
25 ((base_addr_mask) & ((1ULL << (PAGE_SHIFT + (((level) - 1) * (bits_per_level)))) - 1))
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/openbmc/u-boot/arch/arm/cpu/armv8/
H A Dcache_v8.c1 // SPDX-License-Identifier: GPL-2.0+
19 * With 4k page granule, a virtual address is split into 4 lookup parts
26 * 63-48 47-39 38-30 29-21 20-12 11-00
28 * mask page size
30 * Lv0: FF8000000000 --
96 /* Returns the LSB number for a PTE on level <level> */
97 static int level2shift(int level) in level2shift() argument
99 /* Page is 12 bits wide, every level translates 9 bits */ in level2shift()
100 return (12 + 9 * (3 - level)); in level2shift()
103 static u64 *find_pte(u64 addr, int level) in find_pte() argument
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/openbmc/linux/arch/arm64/include/asm/
H A Dkvm_pgtable.h1 // SPDX-License-Identifier: GPL-2.0-only
17 * The largest supported block sizes for KVM (no 52-bit PA support):
18 * - 4K (level 1): 1GB
19 * - 16K (level 2): 32MB
20 * - 64K (level 2): 512MB
45 #define KVM_PHYS_INVALID (-1ULL)
79 static inline u64 kvm_granule_shift(u32 level) in kvm_granule_shift() argument
82 return ARM64_HW_PGTABLE_LEVEL_SHIFT(level); in kvm_granule_shift()
85 static inline u64 kvm_granule_size(u32 level) in kvm_granule_size() argument
87 return BIT(kvm_granule_shift(level)); in kvm_granule_size()
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/openbmc/linux/scripts/gdb/linux/
H A Dpgtable.py1 # SPDX-License-Identifier: GPL-2.0-only
5 # routines to introspect page table
18 def page_mask(level=1): argument
20 if level == 1:
23 elif level == 2:
26 elif level == 3:
29 raise Exception(f'Unknown page level: {level}')
44 return (bit_start, bit_end), data >> bit_start & ((1 << (1 + bit_end - bit_start)) - 1)
46 def entry_va(level, phys_addr, translating_va): argument
47 def start_bit(level): argument
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/openbmc/linux/fs/verity/
H A Dverify.c1 // SPDX-License-Identifier: GPL-2.0
3 * Data verification functions, i.e. hooks for ->readahead()
19 static bool is_hash_block_verified(struct fsverity_info *vi, struct page *hpage, in is_hash_block_verified()
27 * When the Merkle tree block size and page size are the same, then the in is_hash_block_verified()
28 * ->hash_block_verified bitmap isn't allocated, and we use PG_checked in is_hash_block_verified()
29 * to directly indicate whether the page's block has been verified. in is_hash_block_verified()
31 * Using PG_checked also guarantees that we re-verify hash pages that in is_hash_block_verified()
32 * get evicted and re-instantiated from the backing storage, as new in is_hash_block_verified()
35 if (!vi->hash_block_verified) in is_hash_block_verified()
39 * When the Merkle tree block size and page size differ, we use a bitmap in is_hash_block_verified()
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/openbmc/linux/tools/perf/pmu-events/arch/arm64/ampere/emag/
H A Dcache.json78 …"PublicDescription": "Level 2 access to data TLB that caused a page table walk. This event counts …
84 …"PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event …
108 "PublicDescription": "Level 1 data cache late miss",
114 "PublicDescription": "Level 1 data cache prefetch request",
120 "PublicDescription": "Level 2 data cache prefetch request",
126 "PublicDescription": "Level 1 stage 2 TLB refill",
132 "PublicDescription": "Page walk cache level-0 stage-1 hit",
135 "BriefDescription": "Page walk, L0 stage-1 hit"
138 "PublicDescription": "Page walk cache level-1 stage-1 hit",
141 "BriefDescription": "Page walk, L1 stage-1 hit"
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/openbmc/linux/Documentation/virt/kvm/x86/
H A Dmmu.rst1 .. SPDX-License-Identifier: GPL-2.0
13 - correctness:
18 - security:
21 - performance:
23 - scaling:
25 - hardware:
27 - integration:
29 so that swapping, page migration, page merging, transparent
31 - dirty tracking:
33 and framebuffer-based displays
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/openbmc/linux/include/asm-generic/
H A Dpgalloc.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * __pte_alloc_one_kernel - allocate memory for a PTE-level kernel page table
15 * anything beyond simple page allocation.
31 * pte_alloc_one_kernel - allocate memory for a PTE-level kernel page table
43 * pte_free_kernel - free PTE-level kernel page table memory
45 * @pte: pointer to the memory containing the page table
53 * __pte_alloc_one - allocate memory for a PTE-level user page table
57 * Allocate memory for a page table and ptdesc and runs pagetable_pte_ctor().
60 * anything beyond simple page allocation or must have custom GFP flags.
62 * Return: `struct page` referencing the ptdesc or %NULL on error
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/openbmc/linux/fs/f2fs/
H A Ddir.c1 // SPDX-License-Identifier: GPL-2.0
25 return ((unsigned long long) (i_size_read(inode) + PAGE_SIZE - 1)) in dir_blocks()
29 static unsigned int dir_buckets(unsigned int level, int dir_level) in dir_buckets() argument
31 if (level + dir_level < MAX_DIR_HASH_DEPTH / 2) in dir_buckets()
32 return BIT(level + dir_level); in dir_buckets()
37 static unsigned int bucket_blocks(unsigned int level) in bucket_blocks() argument
39 if (level < MAX_DIR_HASH_DEPTH / 2) in bucket_blocks()
45 /* If @dir is casefolded, initialize @fname->cf_name from @fname->usr_fname. */
50 struct super_block *sb = dir->i_sb; in f2fs_init_casefolded_name()
53 !is_dot_dotdot(fname->usr_fname->name, fname->usr_fname->len)) { in f2fs_init_casefolded_name()
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/openbmc/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Dvirtual-memory.json3 …"BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Director…
10 …the number of first level TLB misses but second level hits due to a demand load that did not start…
17 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page…
20 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
25 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G pag…
28 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
33 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or …
36 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
41 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag…
44 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
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/openbmc/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A Dvirtual-memory.json3 …"BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Director…
10 …the number of first level TLB misses but second level hits due to a demand load that did not start…
17 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page…
20 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
25 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G pag…
28 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
33 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or …
36 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
41 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag…
44 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
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/openbmc/linux/drivers/iommu/amd/
H A Dio_pgtable_v2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * CPU-agnostic AMD IO page table v2 allocator.
10 #define pr_fmt(fmt) "AMD-Vi: " fmt
14 #include <linux/io-pgtable.h>
25 #define IOMMU_PAGE_PWT BIT_ULL(3) /* Page write through */
26 #define IOMMU_PAGE_PCD BIT_ULL(4) /* Page cache disabled */
29 #define IOMMU_PAGE_PSE BIT_ULL(7) /* Page Size Extensions */
48 static inline u64 set_pgtable_attr(u64 *page) in set_pgtable_attr() argument
55 return (iommu_virt_to_phys(page) | prot); in set_pgtable_attr()
74 /* Large page */ in set_pte_attr()
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/openbmc/linux/arch/powerpc/include/asm/nohash/64/
H A Dpgtable-4k.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <asm-generic/pgtable-nop4d.h>
8 * Entries per page directory level. The PTE level must use a 64b record
9 * for each page table entry. The PMD and PGD level use a 32b record for
10 * each entry by assuming that each entry is page aligned.
29 /* PMD_SHIFT determines what a second-level page table entry can map */
32 #define PMD_MASK (~(PMD_SIZE-1))
34 /* PUD_SHIFT determines what a third-level page table entry can map */
37 #define PUD_MASK (~(PUD_SIZE-1))
39 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */
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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_vm_pt.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
31 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
37 unsigned int level; member
41 * amdgpu_vm_pt_level_shift - return the addr shift for each level
44 * @level: VMPT level
47 * The number of bits the pfn needs to be right shifted for a level.
50 unsigned int level) in amdgpu_vm_pt_level_shift() argument
52 switch (level) { in amdgpu_vm_pt_level_shift()
56 return 9 * (AMDGPU_VM_PDB0 - level) + in amdgpu_vm_pt_level_shift()
57 adev->vm_manager.block_size; in amdgpu_vm_pt_level_shift()
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/openbmc/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A Dvirtual-memory.json3 …the number of first level TLB misses but second level hits due to a demand load that did not start…
14 …licDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
20 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
24 …ublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page wa…
30 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses.",
38 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
41 …s completed page walks (all page sizes) caused by demand data loads. This implies it missed in th…
47 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
50 …leted page walks (1G sizes) caused by demand data loads. This implies address translations missed…
56 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or …
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/openbmc/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A Dvirtual-memory.json3 "BriefDescription": "Page walk for a large page completed for Demand load.",
10 … load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.",
13 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand…
18 …cription": "Load operations that miss the first DTLB level but hit the second and do not cause pag…
21 … "PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.",
26 …in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page siz…
29 …"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by dema…
34 "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",
42 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
45 … "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
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/openbmc/linux/arch/arc/include/asm/
H A Dpgtable-levels.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 * 2 level paging setup for software walked MMUv3 (ARC700) and MMUv4 (HS)
19 * -------------------------------------------------------
20 * | | <---------- PGDIR_SHIFT ----------> |
21 * | | | <-- PAGE_SHIFT --> |
22 * -------------------------------------------------------
24 * | | --> off in page frame
25 * | ---> index into Page Table
26 * ----> index into Page Directory
29 * However enabling of super page in a 2 level regime pegs PGDIR_SHIFT to
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/openbmc/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Dvirtual-memory.json3 …in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page siz…
10 "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",
17 "BriefDescription": "Page walk for a large page completed for Demand load.",
24 … load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.",
27 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand…
32 …cription": "Load operations that miss the first DTLB level but hit the second and do not cause pag…
35 … "PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.",
40 …in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page siz…
43 …"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by dema…
48 "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",
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/openbmc/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dmarked.json10 …"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond …
20 … Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same …
45 …efDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 d…
50 …efDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 d…
60 …iption": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marke…
70 …Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the sa…
95 …Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the …
100 …Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the sa…
140 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc…
170 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d…
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/openbmc/linux/arch/x86/mm/
H A Dmem_encrypt_amd.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/dma-direct.h>
21 #include <linux/dma-mapping.h>
33 #include <asm/processor-flags.h>
51 /* Buffer used for early in-place encryption by BSP, no locking needed */
55 * SNP-specific routine which needs to additionally change the page state from
66 * @paddr needs to be accessed decrypted, mark the page shared in in snp_memcpy()
73 /* Restore the page state after the memcpy. */ in snp_memcpy()
77 * @paddr need to be accessed encrypted, no need for the page state in snp_memcpy()
86 * page(s) that map this memory. It assumes that eventually the memory is
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/openbmc/linux/arch/x86/mm/pat/
H A Dset_memory.c1 // SPDX-License-Identifier: GPL-2.0-only
35 #include <asm/hyperv-tlfs.h>
41 * The current flushing context - we pass it instead of 5 arguments:
55 struct page **pages;
69 * entries change the page attribute in parallel to some other cpu
70 * splitting a large page entry along with changing the attribute.
87 void update_page_count(int level, unsigned long pages) in update_page_count() argument
91 direct_pages_count[level] += pages; in update_page_count()
95 static void split_page_count(int level) in split_page_count() argument
97 if (direct_pages_count[level] == 0) in split_page_count()
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