Searched +full:p0 +full:- +full:burst +full:- +full:params (Results 1 – 23 of 23) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Piyush Mehta <piyush.mehta@amd.com>14 special extensions to add functionality, is a high-performance dual-port21 const: ceva,ahci-1v8429 dma-coherent: true37 power-domains:40 ceva,p0-cominit-params:[all …]
1 // SPDX-License-Identifier: GPL-2.0-only73 #define DRV_NAME "ahci-ceva"78 MODULE_PARM_DESC(rx_watermark, "RxWaterMark value (0 - 0x80)");124 void __iomem *mmio = hpriv->mmio; in ahci_ceva_setup()125 struct ceva_ahci_priv *cevapriv = hpriv->plat_data; in ahci_ceva_setup()142 * Set Mem Addr Read ID, Write ID for non-data transfers in ahci_ceva_setup()150 if (cevapriv->is_cci_enabled) { in ahci_ceva_setup()164 writel(cevapriv->pp2c[i], mmio + AHCI_VEND_PP2C); in ahci_ceva_setup()167 writel(cevapriv->pp3c[i], mmio + AHCI_VEND_PP3C); in ahci_ceva_setup()169 /* Phy Control Burst timing setting */ in ahci_ceva_setup()[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * (C) Copyright 2017 - 2021, Xilinx, Inc.10 /dts-v1/;13 #include "zynqmp-clk-ccf.dtsi"17 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";27 stdout-path = "serial0:115200n8";43 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */44 #address-cells = <1>;45 #size-cells = <1>;47 spi-tx-bus-width = <4>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * dts file for Xilinx ZynqMP zc1751-xm017-dc35 * (C) Copyright 2016 - 2021, Xilinx, Inc.10 /dts-v1/;13 #include "zynqmp-clk-ccf.dtsi"14 #include <dt-bindings/phy/phy.h>17 model = "ZynqMP zc1751-xm017-dc3 RevA";18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";34 stdout-path = "serial0:115200n8";43 compatible = "fixed-clock";[all …]
1 // SPDX-License-Identifier: GPL-2.05 * (C) Copyright 2020 - 2022, Xilinx, Inc.6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.9 * "A" - A01 board un-modified (NXP)10 * "Y" - A01 board modified with legacy interposer (Nexperia)11 * "Z" - A01 board modified with Diode interposer16 #include <dt-bindings/gpio/gpio.h>17 #include <dt-bindings/net/ti-dp83867.h>18 #include <dt-bindings/phy/phy.h>19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * dts file for Xilinx ZynqMP zc1751-xm015-dc15 * (C) Copyright 2015 - 2022, Xilinx, Inc.6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.11 /dts-v1/;14 #include "zynqmp-clk-ccf.dtsi"15 #include <dt-bindings/phy/phy.h>16 #include <dt-bindings/gpio/gpio.h>17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>20 model = "ZynqMP zc1751-xm015-dc1 RevA";[all …]
1 // SPDX-License-Identifier: GPL-2.05 * (C) Copyright 2017 - 2022, Xilinx, Inc.6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.11 /dts-v1/;14 #include "zynqmp-clk-ccf.dtsi"15 #include <dt-bindings/gpio/gpio.h>16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>17 #include <dt-bindings/phy/phy.h>21 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";38 stdout-path = "serial0:115200n8";[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * (C) Copyright 2017 - 2022, Xilinx, Inc.6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.11 /dts-v1/;14 #include "zynqmp-clk-ccf.dtsi"15 #include <dt-bindings/gpio/gpio.h>16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>17 #include <dt-bindings/phy/phy.h>21 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";38 stdout-path = "serial0:115200n8";[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * (C) Copyright 2017 - 2022, Xilinx, Inc.6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.11 /dts-v1/;14 #include "zynqmp-clk-ccf.dtsi"15 #include <dt-bindings/input/input.h>16 #include <dt-bindings/gpio/gpio.h>17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>18 #include <dt-bindings/phy/phy.h>22 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * (C) Copyright 2016 - 2022, Xilinx, Inc.6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.11 /dts-v1/;14 #include "zynqmp-clk-ccf.dtsi"15 #include <dt-bindings/input/input.h>16 #include <dt-bindings/gpio/gpio.h>17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>18 #include <dt-bindings/phy/phy.h>22 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * (C) Copyright 2015 - 2022, Xilinx, Inc.6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.11 /dts-v1/;14 #include "zynqmp-clk-ccf.dtsi"15 #include <dt-bindings/input/input.h>16 #include <dt-bindings/gpio/gpio.h>17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>18 #include <dt-bindings/phy/phy.h>22 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * (C) Copyright 2017 - 2018, Xilinx, Inc.10 /dts-v1/;13 #include "zynqmp-clk-ccf.dtsi"14 #include <dt-bindings/phy/phy.h>18 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";28 stdout-path = "serial0:115200n8";44 compatible = "m25p80", "spi-flash"; /* 32MB FIXME */45 #address-cells = <1>;46 #size-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * dts file for Xilinx ZynqMP zc1751-xm015-dc15 * (C) Copyright 2015 - 2018, Xilinx, Inc.10 /dts-v1/;13 #include "zynqmp-clk-ccf.dtsi"16 model = "ZynqMP zc1751-xm015-dc1 RevA";17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";33 stdout-path = "serial0:115200n8";76 phy-handle = <&phy0>;77 phy-mode = "rgmii-id";[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * dts file for Xilinx ZynqMP zc1751-xm017-dc35 * (C) Copyright 2016 - 2018, Xilinx, Inc.10 /dts-v1/;13 #include "zynqmp-clk-ccf.dtsi"16 model = "ZynqMP zc1751-xm017-dc3 RevA";17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";34 stdout-path = "serial0:115200n8";77 phy-handle = <&phy0>;78 phy-mode = "rgmii-id";[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * (C) Copyright 2017 - 2018, Xilinx, Inc.10 /dts-v1/;13 #include "zynqmp-clk-ccf.dtsi"14 #include <dt-bindings/gpio/gpio.h>15 #include <dt-bindings/phy/phy.h>19 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";36 stdout-path = "serial0:115200n8";56 phy-handle = <&phy0>;57 phy-mode = "rgmii-id";[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * (C) Copyright 2017 - 2018, Xilinx, Inc.10 /dts-v1/;13 #include "zynqmp-clk-ccf.dtsi"14 #include <dt-bindings/gpio/gpio.h>15 #include <dt-bindings/phy/phy.h>19 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";36 stdout-path = "serial0:115200n8";55 phy-handle = <&phy0>;56 phy-mode = "rgmii-id";[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * (C) Copyright 2017 - 2018, Xilinx, Inc.10 /dts-v1/;13 #include "zynqmp-clk-ccf.dtsi"14 #include <dt-bindings/input/input.h>15 #include <dt-bindings/gpio/gpio.h>16 #include <dt-bindings/phy/phy.h>20 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";37 stdout-path = "serial0:115200n8";47 gpio-keys {[all …]
1 // SPDX-License-Identifier: GPL-2.0+10 /dts-v1/;13 #include "zynqmp-clk-ccf.dtsi"14 #include <dt-bindings/input/input.h>15 #include <dt-bindings/gpio/gpio.h>16 #include <dt-bindings/phy/phy.h>20 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";38 stdout-path = "serial0:115200n8";47 gpio-keys {48 compatible = "gpio-keys";[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * (C) Copyright 2015 - 2018, Xilinx, Inc.10 /dts-v1/;13 #include "zynqmp-clk-ccf.dtsi"14 #include <dt-bindings/input/input.h>15 #include <dt-bindings/gpio/gpio.h>16 #include <dt-bindings/phy/phy.h>20 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";38 stdout-path = "serial0:115200n8";47 gpio-keys {[all …]
2 * Use of this source code is governed by a BSD-style license that can be14 * request: CMD [ P0 P1 P2 ... Pn S ]15 * response: ERR [ P0 P1 P2 ... Pn S ]18 * - CMD is the command code. (defined by EC_CMD_ constants)19 * - ERR is the error code. (defined by EC_RES_ constants)20 * - Px is the optional payload.23 * - S is the checksum which is the sum of all payload bytes.50 /* I/O addresses for host command args and params */53 #define EC_LPC_ADDR_HOST_PARAM 0x804 /* For version 2 params; size is59 /* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff[all …]
... line-size icache-nlines icache-associativity ecache-line-size ecache-nlines ecache-associativity ncaches
1 2024-12-28 20:05:26.116-0600 FINEST t586 Statistics.logIt: Added: '/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/rtnetlink.sh' (ShAnalyzer) (took 79 ms)2 2024-12-28 20:05:26.112-0600 FINER t592 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/qemu',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/qemu/chardev/spice.c'3 2024-12-28 20:05:26.116-0600 FINEST t592 Statistics.logIt: Added: '/openbmc/qemu/chardev/spice.c' (CAnalyzer) (took 33 ms)4 2024-1[all...]
1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'3 2024-12-2[all...]